https://gcc.gnu.org/g:c563fa8f138cf2fc960258662b00fc52887e694a
commit r17-5354-gc563fa8f138cf2fc960258662b00fc52887e694a Author: Takayuki 'January June' Suwa <[email protected]> Date: Mon Oct 19 17:09:22 2026 +0900 xtensa: Modify the zeroing of double-precision FP registers in "-fzero-call-used-regs" to use the asm statement infrastructure It is unnecessary to create a specific unspec enumeration entry or MD insn pattern just for this one instance; the implementation can be simplified by using the asm statement infrastructure, similar to zeroing the BR register. Incidentally, while the presence of an asm statement within a function body can potentially hinder optimization, that is not a concern in this case, as it appears at the very end of the function epilogue. gcc/ChangeLog: * config/xtensa/xtensa.cc (xtensa_zero_call_used_regs): Reimplement the zeroing of double-precision FP registers using the asm statement infrastructure. * config/xtensa/xtensa.md (UNSPEC_CONCAT, movdf_concat): Remove. Diff: --- gcc/config/xtensa/xtensa.cc | 15 ++++++++++++--- gcc/config/xtensa/xtensa.md | 11 ----------- 2 files changed, 12 insertions(+), 14 deletions(-) diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc index ad4515a57aea..d0a5042ba2db 100644 --- a/gcc/config/xtensa/xtensa.cc +++ b/gcc/config/xtensa/xtensa.cc @@ -5693,9 +5693,18 @@ xtensa_zero_call_used_regs (HARD_REG_SET selected_regs) UNKNOWN_LOCATION)); } else if (TARGET_FLOAT64 && FP_REG_P (regno)) - emit_insn (gen_movdf_concat (gen_rtx_REG (DFmode, regno), - gen_rtx_REG (SImode, zeroed_regno), - gen_rtx_REG (SImode, zeroed_regno))); + { + argvec = rtvec_alloc (1); + RTVEC_ELT (argvec, 0) = gen_rtx_REG (SImode, zeroed_regno); + convec = rtvec_alloc (1); + RTVEC_ELT (convec, 0) = gen_rtx_ASM_INPUT (SImode, "r"); + emit_insn (gen_rtx_SET (gen_rtx_REG (DFmode, regno), + gen_rtx_ASM_OPERANDS (DFmode, + "wfrd\t%0, %1, %1", + "f", 0, argvec, convec, + rtvec_alloc (0), + UNKNOWN_LOCATION))); + } else if (TARGET_FLOAT32 && FP_REG_P (regno)) emit_move_insn (gen_rtx_REG (SFmode, regno), gen_rtx_REG (SFmode, zeroed_regno)); diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index 0f5719e0644a..55920b0d5119 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -44,7 +44,6 @@ UNSPEC_CEIL UNSPEC_FLOOR UNSPEC_ROUND - UNSPEC_CONCAT ]) (define_c_enum "unspecv" [ @@ -1635,16 +1634,6 @@ } [(set_attr "mode" "DF")]) -(define_insn "movdf_concat" - [(set (match_operand:DF 0 "register_operand" "=f") - (unspec:DF [(match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "register_operand" "r")] UNSPEC_CONCAT))] - "TARGET_FLOAT64" - "wfrd\t%0, %1, %2" - [(set_attr "type" "farith") - (set_attr "mode" "DF") - (set_attr "length" "3")]) - ;; Block moves (define_expand "cpymemsi"
