https://gcc.gnu.org/g:8cc6e7178c2e3b6156d7992bd18285be0da3c92c
commit r17-5427-g8cc6e7178c2e3b6156d7992bd18285be0da3c92c Author: xiezhiheng <[email protected]> Date: Fri Oct 16 06:26:18 2026 +0000 aarch64: Add missing sve_type for some SVE instructions Since commit fd7c5910162acddf1ae25bad82e4d4447d28ca8d was merged, using -mcpu=hip12 shows a considerable reduction in compile time. However, when building the SPEC benchmark, there are still several cases with a significant increase in compile time. The reason is that some SVE instructions do not have sve_type set, so they cannot be mapped. Add the missing sve_type that I encountered. After updating sve_type, the following test cases fail, all because the order of the "mov z?.d, z?.d" instructions changes. Therefore, I added the -fno-schedule-insns2 option to avoid instruction scheduling affecting the assembly checks. FAIL: gcc.target/aarch64/sve2/acle/asm/dot_lane_mf8.c FAIL: gcc.target/aarch64/sve2/acle/asm/dot_mf8.c FAIL: gcc.target/aarch64/sve2/acle/asm/mlalb_lane_mf8.c FAIL: gcc.target/aarch64/sve2/acle/asm/mlalb_mf8.c FAIL: gcc.target/aarch64/sve2/acle/asm/mlallbb_lane_mf8.c FAIL: gcc.target/aarch64/sve2/acle/asm/mlallbb_mf8.c FAIL: gcc.target/aarch64/sve2/acle/asm/mlallbt_lane_mf8.c FAIL: gcc.target/aarch64/sve2/acle/asm/mlallbt_mf8.c FAIL: gcc.target/aarch64/sve2/acle/asm/mlalltb_lane_mf8.c FAIL: gcc.target/aarch64/sve2/acle/asm/mlalltb_mf8.c FAIL: gcc.target/aarch64/sve2/acle/asm/mlalltt_lane_mf8.c FAIL: gcc.target/aarch64/sve2/acle/asm/mlalltt_mf8.c FAIL: gcc.target/aarch64/sve2/acle/asm/mlalt_lane_mf8.c FAIL: gcc.target/aarch64/sve2/acle/asm/mlalt_mf8.c Bootstrapped and tested on aarch64-linux-gnu. gcc/ChangeLog: * config/aarch64/aarch64-sve.md: Add sve_type for SVE instructions. * config/aarch64/aarch64.md: Likewise. gcc/testsuite/ChangeLog: * g++.target/aarch64/sve2/acle/aarch64-sve2-acle-asm.exp: Add -fno-schedule-insns2 option. * gcc.target/aarch64/sve2/acle/aarch64-sve2-acle-asm.exp: Likewise. * gcc.target/aarch64/sve/pred_clobber_4.c: Adjust instruction order. * gcc.target/aarch64/sve2/acle/asm/pmlal_pair_u64.c: Likewise. Signed-off-by: Zhiheng Xie <[email protected]> Diff: --- gcc/config/aarch64/aarch64-sve.md | 7 +++++-- gcc/config/aarch64/aarch64.md | 1 + .../g++.target/aarch64/sve2/acle/aarch64-sve2-acle-asm.exp | 2 +- gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_4.c | 2 +- .../gcc.target/aarch64/sve2/acle/aarch64-sve2-acle-asm.exp | 2 +- gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/pmlal_pair_u64.c | 4 ++-- 6 files changed, 11 insertions(+), 7 deletions(-) diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md index 015ec68641b1..8d171758a36d 100644 --- a/gcc/config/aarch64/aarch64-sve.md +++ b/gcc/config/aarch64/aarch64-sve.md @@ -702,8 +702,8 @@ {@ [ cons: =0 , 1 ; attrs: sve_type ] [ w , Utr ; sve_load_1reg ] ldr\t%0, %1 [ Utr , w ; sve_store_1reg ] str\t%1, %0 - [ w , w ; * ] mov\t%0.d, %1.d - [ w , Dn ; * ] << aarch64_output_sve_mov_immediate (operands[1]); + [ w , w ; sve_int_general ] mov\t%0.d, %1.d + [ w , Dn ; sve_int_general ] << aarch64_output_sve_mov_immediate (operands[1]); } ) @@ -741,6 +741,7 @@ [ w , w ] mov\t%0.d, %1.d [ w , Dn ] << aarch64_output_sve_mov_immediate (operands[1]); } + [(set_attr "sve_type" "sve_int_general")] ) ;; Handle memory reloads for modes that can't use LDR and STR. We use @@ -2827,6 +2828,7 @@ CONST0_RTX (<MODE>mode))); DONE; } + [(set_attr "sve_type" "sve_int_general")] ) ;; Duplicate an Advanced SIMD vector to fill an SVE vector (LE version). @@ -2905,6 +2907,7 @@ [ w , r ] mov\t%0.<single_type>, %<single_wx>1 [ w , w ] mov\t%0.<single_type>, %<single_type>1 } + [(set_attr "sve_type" "sve_int_general")] ) ;; This is used for vec_duplicate<mode>s from memory, but can also diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 4abf2b7baae6..8d0e50db2722 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -5273,6 +5273,7 @@ { return aarch64_output_sve_cnt_immediate ("uqdec", "%<w>0", operands[2]); } + [(set_attr "sve_type" "sve_pred_cnt_scalar")] ) ;; Implement MAX/MIN (A, B) - C using SUBS/ADDS followed by CSEL/CSINV/CSINC. diff --git a/gcc/testsuite/g++.target/aarch64/sve2/acle/aarch64-sve2-acle-asm.exp b/gcc/testsuite/g++.target/aarch64/sve2/acle/aarch64-sve2-acle-asm.exp index 7ee30a3d7426..c10989cc66c8 100644 --- a/gcc/testsuite/g++.target/aarch64/sve2/acle/aarch64-sve2-acle-asm.exp +++ b/gcc/testsuite/g++.target/aarch64/sve2/acle/aarch64-sve2-acle-asm.exp @@ -59,7 +59,7 @@ set-torture-options { "-std=c++14 -O3 -g" "-std=c++17 -Og -g" "-std=c++2a -Os -g" - "-std=gnu++98 -O2 -fno-schedule-insns -DCHECK_ASM --save-temps" + "-std=gnu++98 -O2 -fno-schedule-insns -fno-schedule-insns2 -DCHECK_ASM --save-temps" "-std=gnu++11 -Ofast -g" "-std=gnu++17 -O3 -g" "-std=gnu++2a -O0 -g" diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_4.c b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_4.c index 73af2a8a3aec..a57bf0e3706c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_4.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/pred_clobber_4.c @@ -11,8 +11,8 @@ extern void use(svbool_t); /* ** foo: ** ... -** ptrue p0.b, all ** mov z[0-9]+.h, w0 +** ptrue p0.b, all ** cmplo p0.h, p0/z, z0.h, z[0-9]+.h ** ... */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/aarch64-sve2-acle-asm.exp b/gcc/testsuite/gcc.target/aarch64/sve2/acle/aarch64-sve2-acle-asm.exp index ffb884db4a08..8713121ce45c 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/aarch64-sve2-acle-asm.exp +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/aarch64-sve2-acle-asm.exp @@ -56,7 +56,7 @@ set-torture-options { "-std=c90 -O1 -g" "-std=c99 -O2 -g" "-std=c11 -O3 -g" - "-std=gnu90 -O2 -fno-schedule-insns -DCHECK_ASM --save-temps" + "-std=gnu90 -O2 -fno-schedule-insns -fno-schedule-insns2 -DCHECK_ASM --save-temps" "-std=gnu99 -Ofast -g" "-std=gnu11 -Os -g" } { diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/pmlal_pair_u64.c b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/pmlal_pair_u64.c index 222832adff33..4474e713261b 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/pmlal_pair_u64.c +++ b/gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/pmlal_pair_u64.c @@ -66,9 +66,9 @@ TEST_XN_INDEXED(test_pmlal_pair_n_u64_regs_x0_1, svuint64x2_t, svuint64_t, /* **test_pmlal_pair_n_u64_regs_mov: -** movi d30, #0 ** mov z0.d, z3.d ** mov z1.d, z4.d +** movi d30, #0 ** pmlal {z0.q - z1.q}, z4.d, z30.d ** ret */ @@ -90,9 +90,9 @@ TEST_XN_INDEXED(test_pmlal_pair_n_u64_regs_mov_x0, svuint64x2_t, svuint64_t, /* **test_pmlal_pair_n_u64_regs_mov_1: -** mov z30.d, #65535 ** mov z0.d, z3.d ** mov z1.d, z4.d +** mov z30.d, #65535 ** pmlal {z0.q - z1.q}, z4.d, z30.d ** ret */
