https://gcc.gnu.org/g:0f54a0b140214ed5e70d78b0bcb7361efe97e973
commit 0f54a0b140214ed5e70d78b0bcb7361efe97e973 Author: Andrew Stubbs <[email protected]> Date: Thu Sep 10 16:47:19 2026 +0000 testsuite, amdgcn: testsuite changes The GCN testcases were written with the assumption that vectorization was always available. With SIMT, this assumption is no longer valid, so this patch adds the appropriate effective target lines. The target-supports.exp settings are adjusted to fix the target-independent test expectations. Assisted-by: Claude Sonnet 5 / Opus 5.5 gcc/testsuite/ChangeLog: * lib/target-supports.exp (check_effective_target_amdgcn_simd): New procedure. (check_effective_target_amdgcn_simt): New procedure. (check_effective_target_vect_int): Use check_effective_target_amdgcn_simd instead of testing for amdgcn directly, because the vector modes only exist in SIMD mode. (check_effective_target_vect_early_break): Likewise. (check_effective_target_vect_early_break_hw): Likewise. (check_effective_target_vect_intfloat_cvt): Likewise. (check_effective_target_vect_uintfloat_cvt): Likewise. (check_effective_target_vect_floatint_cvt): Likewise. (check_effective_target_vect_floatuint_cvt): Likewise. (check_effective_target_vect_simd_clones): Likewise. (check_effective_target_vect_shift): Likewise. (check_effective_target_whole_vector_shift): Likewise. (check_effective_target_vect_bswap): Likewise. (check_effective_target_vect_char_add): Likewise. (check_effective_target_vect_shift_char): Likewise. (check_effective_target_vect_long): Likewise. (check_effective_target_vect_float): Likewise. (check_effective_target_vect_double): Likewise. (check_effective_target_vect_long_long): Likewise. (check_effective_target_vect_perm): Likewise. (check_effective_target_vect_perm_byte): Likewise. (check_effective_target_vect_perm_short): Likewise. (check_effective_target_vect_widen_mult_qi_to_hi): Likewise. (check_effective_target_vect_widen_mult_hi_to_si): Likewise. (check_effective_target_vect_widen_mult_qi_to_hi_pattern): Likewise. (check_effective_target_vect_widen_mult_hi_to_si_pattern): Likewise. (check_effective_target_vect_pack_trunc): Likewise. (check_effective_target_vect_unpack): Likewise. (check_effective_target_vect_hw_misalign): Likewise. (check_effective_target_vect_natural_alignment): Likewise. (check_effective_target_vect_fully_masked): Likewise. (check_effective_target_vect_masked_load): Likewise. (check_effective_target_vect_masked_store): Likewise. (check_effective_target_vect_gather_load_ifn): Likewise. (check_effective_target_vect_scatter_store): Likewise. (check_effective_target_vect_condition): Likewise. (check_effective_target_vect_cond_mixed): Likewise. (check_effective_target_vect_char_mult): Likewise. (check_effective_target_vect_short_mult): Likewise. (check_effective_target_vect_int_mult): Likewise. (check_effective_target_vect_long_mult): Likewise. (check_effective_target_vect_call_copysignf): Likewise. (check_effective_target_vect_call_sqrtf): Likewise. (check_effective_target_vect_call_lrint): Likewise. (check_effective_target_vect_call_btrunc): Likewise. (check_effective_target_vect_call_btruncf): Likewise. (check_effective_target_vect_call_ceil): Likewise. (check_effective_target_vect_call_ceilf): Likewise. (check_effective_target_vect_call_floor): Likewise. (check_effective_target_vect_call_floorf): Likewise. (check_effective_target_vect_logical_reduc): Likewise. (check_effective_target_vect_fold_extract_last): Likewise. (check_vect_support_and_set_flags): Do not run the vectorizer tests on amdgcn in SIMT mode. * gcc.target/gcn/avgpr-spill-double.c: Require vect_double. * gcc.target/gcn/avgpr-spill-int.c: Require vect_int. * gcc.target/gcn/avgpr-spill-long.c: Likewise. * gcc.target/gcn/avgpr-spill-short.c: Likewise. * gcc.target/gcn/cond_fmaxnm_1.c: Require vect_float and vect_double. * gcc.target/gcn/cond_fmaxnm_1_run.c: Likewise. * gcc.target/gcn/cond_fmaxnm_2.c: Likewise. * gcc.target/gcn/cond_fmaxnm_2_run.c: Likewise. * gcc.target/gcn/cond_fmaxnm_3.c: Likewise. * gcc.target/gcn/cond_fmaxnm_3_run.c: Likewise. * gcc.target/gcn/cond_fmaxnm_4.c: Likewise. * gcc.target/gcn/cond_fmaxnm_4_run.c: Likewise. * gcc.target/gcn/cond_fmaxnm_5.c: Likewise. * gcc.target/gcn/cond_fmaxnm_5_run.c: Likewise. * gcc.target/gcn/cond_fmaxnm_6.c: Likewise. * gcc.target/gcn/cond_fmaxnm_6_run.c: Likewise. * gcc.target/gcn/cond_fmaxnm_7.c: Likewise. * gcc.target/gcn/cond_fmaxnm_7_run.c: Likewise. * gcc.target/gcn/cond_fmaxnm_8.c: Likewise. * gcc.target/gcn/cond_fmaxnm_8_run.c: Likewise. * gcc.target/gcn/cond_fminnm_1.c: Likewise. * gcc.target/gcn/cond_fminnm_1_run.c: Likewise. * gcc.target/gcn/cond_fminnm_2.c: Likewise. * gcc.target/gcn/cond_fminnm_2_run.c: Likewise. * gcc.target/gcn/cond_fminnm_3.c: Likewise. * gcc.target/gcn/cond_fminnm_3_run.c: Likewise. * gcc.target/gcn/cond_fminnm_4.c: Likewise. * gcc.target/gcn/cond_fminnm_4_run.c: Likewise. * gcc.target/gcn/cond_fminnm_5.c: Likewise. * gcc.target/gcn/cond_fminnm_5_run.c: Likewise. * gcc.target/gcn/cond_fminnm_6.c: Likewise. * gcc.target/gcn/cond_fminnm_6_run.c: Likewise. * gcc.target/gcn/cond_fminnm_7.c: Likewise. * gcc.target/gcn/cond_fminnm_7_run.c: Likewise. * gcc.target/gcn/cond_fminnm_8.c: Likewise. * gcc.target/gcn/cond_fminnm_8_run.c: Likewise. * gcc.target/gcn/cond_shift_3.c: Require vect_int. * gcc.target/gcn/cond_shift_3_run.c: Likewise. * gcc.target/gcn/cond_shift_4.c: Likewise. * gcc.target/gcn/cond_shift_4_run.c: Likewise. * gcc.target/gcn/cond_shift_8.c: Likewise. * gcc.target/gcn/cond_shift_8_run.c: Likewise. * gcc.target/gcn/cond_shift_9.c: Likewise. * gcc.target/gcn/cond_shift_9_run.c: Likewise. * gcc.target/gcn/cond_smax_1.c: Likewise. * gcc.target/gcn/cond_smax_1_run.c: Likewise. * gcc.target/gcn/cond_smin_1.c: Likewise. * gcc.target/gcn/cond_smin_1_run.c: Likewise. * gcc.target/gcn/cond_umax_1.c: Likewise. * gcc.target/gcn/cond_umax_1_run.c: Likewise. * gcc.target/gcn/cond_umin_1.c: Likewise. * gcc.target/gcn/cond_umin_1_run.c: Likewise. * gcc.target/gcn/math-builtins-1.c: Require vect_float and vect_double. * gcc.target/gcn/sgpr-spill-double.c: Require amdgcn_simd, and say why. * gcc.target/gcn/sgpr-spill-int.c: Likewise. * gcc.target/gcn/sgpr-spill-long.c: Likewise. * gcc.target/gcn/sgpr-spill-short.c: Likewise. * gcc.target/gcn/simd-math-1.c: Require vect_float and vect_double. * gcc.target/gcn/simd-math-2.c: Likewise. * gcc.target/gcn/simd-math-3-16.c: Require vect_int. * gcc.target/gcn/simd-math-3-2.c: Likewise. * gcc.target/gcn/simd-math-3-32.c: Likewise. * gcc.target/gcn/simd-math-3-4.c: Likewise. * gcc.target/gcn/simd-math-3-8.c: Likewise. * gcc.target/gcn/simd-math-3-char-16.c: Likewise. * gcc.target/gcn/simd-math-3-char-2.c: Likewise. * gcc.target/gcn/simd-math-3-char-32.c: Likewise. * gcc.target/gcn/simd-math-3-char-4.c: Likewise. * gcc.target/gcn/simd-math-3-char-8.c: Likewise. * gcc.target/gcn/simd-math-3-char-run-16.c: Likewise. * gcc.target/gcn/simd-math-3-char-run-2.c: Likewise. * gcc.target/gcn/simd-math-3-char-run-32.c: Likewise. * gcc.target/gcn/simd-math-3-char-run-4.c: Likewise. * gcc.target/gcn/simd-math-3-char-run-8.c: Likewise. * gcc.target/gcn/simd-math-3-char-run.c: Likewise. * gcc.target/gcn/simd-math-3-char.c: Likewise. * gcc.target/gcn/simd-math-3-long-16.c: Likewise. * gcc.target/gcn/simd-math-3-long-2.c: Likewise. * gcc.target/gcn/simd-math-3-long-32.c: Likewise. * gcc.target/gcn/simd-math-3-long-4.c: Likewise. * gcc.target/gcn/simd-math-3-long-8.c: Likewise. * gcc.target/gcn/simd-math-3-long-run-16.c: Likewise. * gcc.target/gcn/simd-math-3-long-run-2.c: Likewise. * gcc.target/gcn/simd-math-3-long-run-32.c: Likewise. * gcc.target/gcn/simd-math-3-long-run-4.c: Likewise. * gcc.target/gcn/simd-math-3-long-run-8.c: Likewise. * gcc.target/gcn/simd-math-3-long-run.c: Likewise. * gcc.target/gcn/simd-math-3-long.c: Likewise. * gcc.target/gcn/simd-math-3-run-16.c: Likewise. * gcc.target/gcn/simd-math-3-run-2.c: Likewise. * gcc.target/gcn/simd-math-3-run-32.c: Likewise. * gcc.target/gcn/simd-math-3-run-4.c: Likewise. * gcc.target/gcn/simd-math-3-run-8.c: Likewise. * gcc.target/gcn/simd-math-3-run.c: Likewise. * gcc.target/gcn/simd-math-3-short-16.c: Likewise. * gcc.target/gcn/simd-math-3-short-2.c: Likewise. * gcc.target/gcn/simd-math-3-short-32.c: Likewise. * gcc.target/gcn/simd-math-3-short-4.c: Likewise. * gcc.target/gcn/simd-math-3-short-8.c: Likewise. * gcc.target/gcn/simd-math-3-short-run-16.c: Likewise. * gcc.target/gcn/simd-math-3-short-run-2.c: Likewise. * gcc.target/gcn/simd-math-3-short-run-32.c: Likewise. * gcc.target/gcn/simd-math-3-short-run-4.c: Likewise. * gcc.target/gcn/simd-math-3-short-run-8.c: Likewise. * gcc.target/gcn/simd-math-3-short-run.c: Likewise. * gcc.target/gcn/simd-math-3-short.c: Likewise. * gcc.target/gcn/simd-math-3.c: Likewise. * gcc.target/gcn/simd-math-4-char-run.c: Likewise. * gcc.target/gcn/simd-math-4-char.c: Likewise. * gcc.target/gcn/simd-math-4-long-run.c: Likewise. * gcc.target/gcn/simd-math-4-long.c: Likewise. * gcc.target/gcn/simd-math-4-run.c: Likewise. * gcc.target/gcn/simd-math-4-short-run.c: Likewise. * gcc.target/gcn/simd-math-4-short.c: Likewise. * gcc.target/gcn/simd-math-4.c: Likewise. * gcc.target/gcn/simd-math-5-16.c: Likewise. * gcc.target/gcn/simd-math-5-32.c: Likewise. * gcc.target/gcn/simd-math-5-4.c: Likewise. * gcc.target/gcn/simd-math-5-8.c: Likewise. * gcc.target/gcn/simd-math-5-char-16.c: Likewise. * gcc.target/gcn/simd-math-5-char-32.c: Likewise. * gcc.target/gcn/simd-math-5-char-4.c: Likewise. * gcc.target/gcn/simd-math-5-char-8.c: Likewise. * gcc.target/gcn/simd-math-5-char-run-16.c: Likewise. * gcc.target/gcn/simd-math-5-char-run-32.c: Likewise. * gcc.target/gcn/simd-math-5-char-run-4.c: Likewise. * gcc.target/gcn/simd-math-5-char-run-8.c: Likewise. * gcc.target/gcn/simd-math-5-char-run.c: Likewise. * gcc.target/gcn/simd-math-5-char.c: Likewise. * gcc.target/gcn/simd-math-5-long-16.c: Likewise. * gcc.target/gcn/simd-math-5-long-32.c: Likewise. * gcc.target/gcn/simd-math-5-long-4.c: Likewise. * gcc.target/gcn/simd-math-5-long-8.c: Likewise. * gcc.target/gcn/simd-math-5-long-run-16.c: Likewise. * gcc.target/gcn/simd-math-5-long-run-32.c: Likewise. * gcc.target/gcn/simd-math-5-long-run-4.c: Likewise. * gcc.target/gcn/simd-math-5-long-run-8.c: Likewise. * gcc.target/gcn/simd-math-5-long-run.c: Likewise. * gcc.target/gcn/simd-math-5-long.c: Likewise. * gcc.target/gcn/simd-math-5-run-16.c: Likewise. * gcc.target/gcn/simd-math-5-run-32.c: Likewise. * gcc.target/gcn/simd-math-5-run-4.c: Likewise. * gcc.target/gcn/simd-math-5-run-8.c: Likewise. * gcc.target/gcn/simd-math-5-run.c: Likewise. * gcc.target/gcn/simd-math-5-short-16.c: Likewise. * gcc.target/gcn/simd-math-5-short-32.c: Likewise. * gcc.target/gcn/simd-math-5-short-4.c: Likewise. * gcc.target/gcn/simd-math-5-short-8.c: Likewise. * gcc.target/gcn/simd-math-5-short-run-16.c: Likewise. * gcc.target/gcn/simd-math-5-short-run-32.c: Likewise. * gcc.target/gcn/simd-math-5-short-run-4.c: Likewise. * gcc.target/gcn/simd-math-5-short-run-8.c: Likewise. * gcc.target/gcn/simd-math-5-short-run.c: Likewise. * gcc.target/gcn/simd-math-5-short.c: Likewise. * gcc.target/gcn/simd-math-5.c: Likewise. * gcc.target/gcn/smax_1.c: Likewise. * gcc.target/gcn/smax_1_run.c: Likewise. * gcc.target/gcn/smin_1.c: Likewise. * gcc.target/gcn/smin_1_run.c: Likewise. * gcc.target/gcn/sram-ecc-3.c: Likewise. * gcc.target/gcn/sram-ecc-4.c: Likewise. * gcc.target/gcn/sram-ecc-7.c: Likewise. * gcc.target/gcn/sram-ecc-8.c: Likewise. * gcc.target/gcn/umax_1.c: Likewise. * gcc.target/gcn/umax_1_run.c: Likewise. * gcc.target/gcn/umin_1.c: Likewise. * gcc.target/gcn/umin_1_run.c: Likewise. * gcc.target/gcn/vcc-clobber.c: Likewise. Diff: --- gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c | 1 + gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c | 1 + gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c | 1 + gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c | 1 + gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1_run.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2_run.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3_run.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4_run.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5_run.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6_run.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7_run.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8_run.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fminnm_1_run.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fminnm_2_run.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fminnm_3_run.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fminnm_4_run.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fminnm_5_run.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fminnm_6_run.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fminnm_7_run.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c | 2 + gcc/testsuite/gcc.target/gcn/cond_fminnm_8_run.c | 2 + gcc/testsuite/gcc.target/gcn/cond_shift_3.c | 1 + gcc/testsuite/gcc.target/gcn/cond_shift_3_run.c | 1 + gcc/testsuite/gcc.target/gcn/cond_shift_4.c | 1 + gcc/testsuite/gcc.target/gcn/cond_shift_4_run.c | 1 + gcc/testsuite/gcc.target/gcn/cond_shift_8.c | 1 + gcc/testsuite/gcc.target/gcn/cond_shift_8_run.c | 1 + gcc/testsuite/gcc.target/gcn/cond_shift_9.c | 1 + gcc/testsuite/gcc.target/gcn/cond_shift_9_run.c | 1 + gcc/testsuite/gcc.target/gcn/cond_smax_1.c | 1 + gcc/testsuite/gcc.target/gcn/cond_smax_1_run.c | 1 + gcc/testsuite/gcc.target/gcn/cond_smin_1.c | 1 + gcc/testsuite/gcc.target/gcn/cond_smin_1_run.c | 1 + gcc/testsuite/gcc.target/gcn/cond_umax_1.c | 1 + gcc/testsuite/gcc.target/gcn/cond_umax_1_run.c | 1 + gcc/testsuite/gcc.target/gcn/cond_umin_1.c | 1 + gcc/testsuite/gcc.target/gcn/cond_umin_1_run.c | 1 + gcc/testsuite/gcc.target/gcn/math-builtins-1.c | 2 + gcc/testsuite/gcc.target/gcn/sgpr-spill-double.c | 5 + gcc/testsuite/gcc.target/gcn/sgpr-spill-int.c | 5 + gcc/testsuite/gcc.target/gcn/sgpr-spill-long.c | 5 + gcc/testsuite/gcc.target/gcn/sgpr-spill-short.c | 5 + gcc/testsuite/gcc.target/gcn/simd-math-1.c | 2 + gcc/testsuite/gcc.target/gcn/simd-math-2.c | 2 + gcc/testsuite/gcc.target/gcn/simd-math-3-16.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-2.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-32.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-4.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-8.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-char-16.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-char-2.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-char-32.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-char-4.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-char-8.c | 1 + .../gcc.target/gcn/simd-math-3-char-run-16.c | 1 + .../gcc.target/gcn/simd-math-3-char-run-2.c | 1 + .../gcc.target/gcn/simd-math-3-char-run-32.c | 1 + .../gcc.target/gcn/simd-math-3-char-run-4.c | 1 + .../gcc.target/gcn/simd-math-3-char-run-8.c | 1 + .../gcc.target/gcn/simd-math-3-char-run.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-char.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-long-16.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-long-2.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-long-32.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-long-4.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-long-8.c | 1 + .../gcc.target/gcn/simd-math-3-long-run-16.c | 1 + .../gcc.target/gcn/simd-math-3-long-run-2.c | 1 + .../gcc.target/gcn/simd-math-3-long-run-32.c | 1 + .../gcc.target/gcn/simd-math-3-long-run-4.c | 1 + .../gcc.target/gcn/simd-math-3-long-run-8.c | 1 + .../gcc.target/gcn/simd-math-3-long-run.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-long.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-run-16.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-run-2.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-run-32.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-run-4.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-run-8.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-run.c | 1 + .../gcc.target/gcn/simd-math-3-short-16.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-short-2.c | 1 + .../gcc.target/gcn/simd-math-3-short-32.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-short-4.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-short-8.c | 1 + .../gcc.target/gcn/simd-math-3-short-run-16.c | 1 + .../gcc.target/gcn/simd-math-3-short-run-2.c | 1 + .../gcc.target/gcn/simd-math-3-short-run-32.c | 1 + .../gcc.target/gcn/simd-math-3-short-run-4.c | 1 + .../gcc.target/gcn/simd-math-3-short-run-8.c | 1 + .../gcc.target/gcn/simd-math-3-short-run.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3-short.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-3.c | 2 + .../gcc.target/gcn/simd-math-4-char-run.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-4-char.c | 1 + .../gcc.target/gcn/simd-math-4-long-run.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-4-long.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-4-run.c | 1 + .../gcc.target/gcn/simd-math-4-short-run.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-4-short.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-4.c | 2 + gcc/testsuite/gcc.target/gcn/simd-math-5-16.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-5-32.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-5-4.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-5-8.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-5-char-16.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-5-char-32.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-5-char-4.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-5-char-8.c | 1 + .../gcc.target/gcn/simd-math-5-char-run-16.c | 1 + .../gcc.target/gcn/simd-math-5-char-run-32.c | 1 + .../gcc.target/gcn/simd-math-5-char-run-4.c | 1 + .../gcc.target/gcn/simd-math-5-char-run-8.c | 1 + .../gcc.target/gcn/simd-math-5-char-run.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-5-char.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-5-long-16.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-5-long-32.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-5-long-4.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-5-long-8.c | 1 + .../gcc.target/gcn/simd-math-5-long-run-16.c | 1 + .../gcc.target/gcn/simd-math-5-long-run-32.c | 1 + .../gcc.target/gcn/simd-math-5-long-run-4.c | 1 + .../gcc.target/gcn/simd-math-5-long-run-8.c | 1 + .../gcc.target/gcn/simd-math-5-long-run.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-5-long.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-5-run-16.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-5-run-32.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-5-run-4.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-5-run-8.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-5-run.c | 1 + .../gcc.target/gcn/simd-math-5-short-16.c | 1 + .../gcc.target/gcn/simd-math-5-short-32.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-5-short-4.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-5-short-8.c | 1 + .../gcc.target/gcn/simd-math-5-short-run-16.c | 1 + .../gcc.target/gcn/simd-math-5-short-run-32.c | 1 + .../gcc.target/gcn/simd-math-5-short-run-4.c | 1 + .../gcc.target/gcn/simd-math-5-short-run-8.c | 1 + .../gcc.target/gcn/simd-math-5-short-run.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-5-short.c | 1 + gcc/testsuite/gcc.target/gcn/simd-math-5.c | 1 + gcc/testsuite/gcc.target/gcn/smax_1.c | 1 + gcc/testsuite/gcc.target/gcn/smax_1_run.c | 1 + gcc/testsuite/gcc.target/gcn/smin_1.c | 1 + gcc/testsuite/gcc.target/gcn/smin_1_run.c | 1 + gcc/testsuite/gcc.target/gcn/sram-ecc-3.c | 1 + gcc/testsuite/gcc.target/gcn/sram-ecc-4.c | 1 + gcc/testsuite/gcc.target/gcn/sram-ecc-7.c | 1 + gcc/testsuite/gcc.target/gcn/sram-ecc-8.c | 1 + gcc/testsuite/gcc.target/gcn/umax_1.c | 1 + gcc/testsuite/gcc.target/gcn/umax_1_run.c | 1 + gcc/testsuite/gcc.target/gcn/umin_1.c | 1 + gcc/testsuite/gcc.target/gcn/umin_1_run.c | 1 + gcc/testsuite/gcc.target/gcn/vcc-clobber.c | 1 + gcc/testsuite/lib/target-supports.exp | 131 +++++++++++++-------- 169 files changed, 302 insertions(+), 50 deletions(-) diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c b/gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c index 3015f8ec6bb8..02a6d61cf56e 100644 --- a/gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c +++ b/gcc/testsuite/gcc.target/gcn/avgpr-spill-double.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=gfx908 -O1" } */ +/* { dg-require-effective-target vect_double } */ /* { dg-final { scan-assembler "accvgpr" } } */ typedef double v32df __attribute__ ((__vector_size__ (sizeof(double)*32))); diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c b/gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c index 887ed4daf959..ce9cfece4c9d 100644 --- a/gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c +++ b/gcc/testsuite/gcc.target/gcn/avgpr-spill-int.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=gfx908 -O1" } */ +/* { dg-require-effective-target vect_int } */ /* { dg-final { scan-assembler "accvgpr" } } */ typedef int v32si __attribute__ ((__vector_size__ (sizeof(int)*32))); diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c b/gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c index 1926fd9df0b4..42eb6dab35bb 100644 --- a/gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c +++ b/gcc/testsuite/gcc.target/gcn/avgpr-spill-long.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=gfx908 -O1" } */ +/* { dg-require-effective-target vect_int } */ /* { dg-final { scan-assembler "accvgpr" } } */ typedef long v32di __attribute__ ((__vector_size__ (sizeof(long)*32))); diff --git a/gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c b/gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c index 71032e7674fd..715e87208f9c 100644 --- a/gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c +++ b/gcc/testsuite/gcc.target/gcn/avgpr-spill-short.c @@ -1,5 +1,6 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=gfx908 -O1" } */ +/* { dg-require-effective-target vect_int } */ /* { dg-final { scan-assembler "accvgpr" } } */ typedef short v32hi __attribute__ ((__vector_size__ (sizeof(short)*32))); diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c index 29e77064bc50..7e0dd99057c0 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1.c @@ -2,6 +2,8 @@ /* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #include <stdint.h> diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1_run.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1_run.c index 1e4c81c17a94..793b0fe944e8 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1_run.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_1_run.c @@ -1,5 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #include "cond_fmaxnm_1.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c index f781ca2c0133..fcc85fd008b3 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2.c @@ -2,6 +2,8 @@ /* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #include <stdint.h> diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2_run.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2_run.c index 05d18f41f067..a78a54326d3c 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2_run.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_2_run.c @@ -1,5 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #include "cond_fmaxnm_2.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c index 0f1fcfbb149f..58a1ea19a97e 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3.c @@ -2,6 +2,8 @@ /* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #include <stdint.h> diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3_run.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3_run.c index 23dd00b0b130..66656042c232 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3_run.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_3_run.c @@ -1,5 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #include "cond_fmaxnm_3.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c index 7885808bca3d..fd2994f03937 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4.c @@ -2,6 +2,8 @@ /* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #include <stdint.h> diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4_run.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4_run.c index 1db583242bae..5e8731ff5605 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4_run.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_4_run.c @@ -1,5 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #include "cond_fmaxnm_4.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c index 6bfc2b9627f2..9d021042ee2c 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5.c @@ -2,6 +2,8 @@ /* { dg-options "-O2 -ftree-vectorize -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #include "cond_fmaxnm_1.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5_run.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5_run.c index 8c0bc2ae876e..ea1ee8881f59 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5_run.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_5_run.c @@ -1,4 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #include "cond_fmaxnm_1_run.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c index 8ea52725cbee..f0eb88465f50 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6.c @@ -2,6 +2,8 @@ /* { dg-options "-O2 -ftree-vectorize -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #include "cond_fmaxnm_2.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6_run.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6_run.c index 5c5db46b3908..12f6929f5c81 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6_run.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_6_run.c @@ -1,4 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #include "cond_fmaxnm_2_run.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c index 97f8cf57ee32..36c0d65f93c2 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7.c @@ -2,6 +2,8 @@ /* { dg-options "-O2 -ftree-vectorize -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #include "cond_fmaxnm_3.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7_run.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7_run.c index 0abe626fdfb0..bfceb361809f 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7_run.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_7_run.c @@ -1,4 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #include "cond_fmaxnm_3_run.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c index 9de89790a123..66ec4a7aba9c 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8.c @@ -2,6 +2,8 @@ /* { dg-options "-O2 -ftree-vectorize -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #include "cond_fmaxnm_4.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8_run.c b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8_run.c index 43b892f922e0..1b838b3f8331 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8_run.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fmaxnm_8_run.c @@ -1,4 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #include "cond_fmaxnm_4_run.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c index 7068e8c4f540..c6ae78f785a1 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_1.c @@ -2,6 +2,8 @@ /* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #define FN(X) __builtin_fmin##X #include "cond_fmaxnm_1.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_1_run.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_1_run.c index 6dd9d499b35b..f217f784a5c8 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_1_run.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_1_run.c @@ -1,5 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #define FN(X) __builtin_fmin##X #include "cond_fmaxnm_1_run.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c index d8ee9446e380..df4c85e58338 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_2.c @@ -2,6 +2,8 @@ /* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #define FN(X) __builtin_fmin##X #include "cond_fmaxnm_2.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_2_run.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_2_run.c index 727842901131..fac8b59d74d4 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_2_run.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_2_run.c @@ -1,5 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #define FN(X) __builtin_fmin##X #include "cond_fmaxnm_2_run.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c index 45b63c088147..ab7fa6682327 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_3.c @@ -2,6 +2,8 @@ /* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #define FN(X) __builtin_fmin##X #include "cond_fmaxnm_3.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_3_run.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_3_run.c index 8c994cae2029..1d955ac3c76f 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_3_run.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_3_run.c @@ -1,5 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #define FN(X) __builtin_fmin##X #include "cond_fmaxnm_3_run.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c index bf41cc615a34..c3c348cc2f95 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_4.c @@ -2,6 +2,8 @@ /* { dg-options "-O2 -ftree-vectorize -ffast-math -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #define FN(X) __builtin_fmin##X #include "cond_fmaxnm_4.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_4_run.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_4_run.c index 728f4136015e..31c1ef48d377 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_4_run.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_4_run.c @@ -1,5 +1,7 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize -ffast-math" } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #define FN(X) __builtin_fmin##X #include "cond_fmaxnm_4_run.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c index 84ab917043da..c15a7cda8154 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_5.c @@ -2,6 +2,8 @@ /* { dg-options "-O2 -ftree-vectorize -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #define FN(X) __builtin_fmin##X #include "cond_fmaxnm_1.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_5_run.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_5_run.c index 9236ab5b211b..c2cda7d6f9cc 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_5_run.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_5_run.c @@ -1,4 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #include "cond_fminnm_1_run.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c index a1525d91b332..c6cd6807daae 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_6.c @@ -2,6 +2,8 @@ /* { dg-options "-O2 -ftree-vectorize -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #define FN(X) __builtin_fmin##X #include "cond_fmaxnm_2.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_6_run.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_6_run.c index a5f90d9e76af..a1d8382d1bde 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_6_run.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_6_run.c @@ -1,4 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #include "cond_fminnm_2_run.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c index bb5e0f24d5bb..d4fae063cb4d 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_7.c @@ -2,6 +2,8 @@ /* { dg-options "-O2 -ftree-vectorize -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #define FN(X) __builtin_fmin##X #include "cond_fmaxnm_3.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_7_run.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_7_run.c index d7ad738db5ce..c50888bd707c 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_7_run.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_7_run.c @@ -1,4 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #include "cond_fminnm_3_run.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c index c090377c0e18..26c4232c6fae 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_8.c @@ -2,6 +2,8 @@ /* { dg-options "-O2 -ftree-vectorize -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #define FN(X) __builtin_fmin##X #include "cond_fmaxnm_4.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_fminnm_8_run.c b/gcc/testsuite/gcc.target/gcn/cond_fminnm_8_run.c index 3d92353ac554..5db747b0a825 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_fminnm_8_run.c +++ b/gcc/testsuite/gcc.target/gcn/cond_fminnm_8_run.c @@ -1,4 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #include "cond_fminnm_4_run.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_shift_3.c b/gcc/testsuite/gcc.target/gcn/cond_shift_3.c index 1181384a4957..1b5899fc9856 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_shift_3.c +++ b/gcc/testsuite/gcc.target/gcn/cond_shift_3.c @@ -2,6 +2,7 @@ /* { dg-options "-O2 -ftree-vectorize -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_int } */ #include <stdint.h> diff --git a/gcc/testsuite/gcc.target/gcn/cond_shift_3_run.c b/gcc/testsuite/gcc.target/gcn/cond_shift_3_run.c index 8f89918e8ac8..b53dcb0fbb74 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_shift_3_run.c +++ b/gcc/testsuite/gcc.target/gcn/cond_shift_3_run.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-require-effective-target vect_int } */ #include "cond_shift_3.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_shift_4.c b/gcc/testsuite/gcc.target/gcn/cond_shift_4.c index ea2110d0a6fe..627389318377 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_shift_4.c +++ b/gcc/testsuite/gcc.target/gcn/cond_shift_4.c @@ -2,6 +2,7 @@ /* { dg-options "-O2 -ftree-vectorize -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_int } */ #include <stdint.h> diff --git a/gcc/testsuite/gcc.target/gcn/cond_shift_4_run.c b/gcc/testsuite/gcc.target/gcn/cond_shift_4_run.c index 6017d68e8201..6b89c7272e6e 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_shift_4_run.c +++ b/gcc/testsuite/gcc.target/gcn/cond_shift_4_run.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-require-effective-target vect_int } */ #include "cond_shift_4.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_shift_8.c b/gcc/testsuite/gcc.target/gcn/cond_shift_8.c index 9942a2e167ce..d4248c934770 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_shift_8.c +++ b/gcc/testsuite/gcc.target/gcn/cond_shift_8.c @@ -2,6 +2,7 @@ /* { dg-options "-O2 -ftree-vectorize -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_int } */ #include <stdint.h> diff --git a/gcc/testsuite/gcc.target/gcn/cond_shift_8_run.c b/gcc/testsuite/gcc.target/gcn/cond_shift_8_run.c index 13da01975693..5f9e9c5d9f6d 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_shift_8_run.c +++ b/gcc/testsuite/gcc.target/gcn/cond_shift_8_run.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-require-effective-target vect_int } */ #include "cond_shift_8.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_shift_9.c b/gcc/testsuite/gcc.target/gcn/cond_shift_9.c index 663192f97e78..dcce492591d3 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_shift_9.c +++ b/gcc/testsuite/gcc.target/gcn/cond_shift_9.c @@ -2,6 +2,7 @@ /* { dg-options "-O2 -ftree-vectorize -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_int } */ #include <stdint.h> diff --git a/gcc/testsuite/gcc.target/gcn/cond_shift_9_run.c b/gcc/testsuite/gcc.target/gcn/cond_shift_9_run.c index de8e010bdab5..7bd03d4ba441 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_shift_9_run.c +++ b/gcc/testsuite/gcc.target/gcn/cond_shift_9_run.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-require-effective-target vect_int } */ #include "cond_shift_9.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_smax_1.c b/gcc/testsuite/gcc.target/gcn/cond_smax_1.c index 212091a15df7..d5c3a08f97b2 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_smax_1.c +++ b/gcc/testsuite/gcc.target/gcn/cond_smax_1.c @@ -2,6 +2,7 @@ /* { dg-options "-O2 -ftree-vectorize -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_int } */ #include <stdint.h> diff --git a/gcc/testsuite/gcc.target/gcn/cond_smax_1_run.c b/gcc/testsuite/gcc.target/gcn/cond_smax_1_run.c index c951e6145791..1d818c346b89 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_smax_1_run.c +++ b/gcc/testsuite/gcc.target/gcn/cond_smax_1_run.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-require-effective-target vect_int } */ #include "cond_smax_1.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_smin_1.c b/gcc/testsuite/gcc.target/gcn/cond_smin_1.c index 714aab2f7f77..adf586de79b6 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_smin_1.c +++ b/gcc/testsuite/gcc.target/gcn/cond_smin_1.c @@ -2,6 +2,7 @@ /* { dg-options "-O2 -ftree-vectorize -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_int } */ #include <stdint.h> diff --git a/gcc/testsuite/gcc.target/gcn/cond_smin_1_run.c b/gcc/testsuite/gcc.target/gcn/cond_smin_1_run.c index bfdb7d1b9e89..6c8c3ba257ea 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_smin_1_run.c +++ b/gcc/testsuite/gcc.target/gcn/cond_smin_1_run.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-require-effective-target vect_int } */ #include "cond_smin_1.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_umax_1.c b/gcc/testsuite/gcc.target/gcn/cond_umax_1.c index 9018b0068176..405174288c54 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_umax_1.c +++ b/gcc/testsuite/gcc.target/gcn/cond_umax_1.c @@ -2,6 +2,7 @@ /* { dg-options "-O2 -ftree-vectorize -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_int } */ #include <stdint.h> diff --git a/gcc/testsuite/gcc.target/gcn/cond_umax_1_run.c b/gcc/testsuite/gcc.target/gcn/cond_umax_1_run.c index 2396c2452d71..15e7f69221c2 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_umax_1_run.c +++ b/gcc/testsuite/gcc.target/gcn/cond_umax_1_run.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-require-effective-target vect_int } */ #include "cond_umax_1.c" diff --git a/gcc/testsuite/gcc.target/gcn/cond_umin_1.c b/gcc/testsuite/gcc.target/gcn/cond_umin_1.c index 64d0a5eb3504..fd3830c8fcb9 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_umin_1.c +++ b/gcc/testsuite/gcc.target/gcn/cond_umin_1.c @@ -2,6 +2,7 @@ /* { dg-options "-O2 -ftree-vectorize -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_int } */ #include <stdint.h> diff --git a/gcc/testsuite/gcc.target/gcn/cond_umin_1_run.c b/gcc/testsuite/gcc.target/gcn/cond_umin_1_run.c index ef6f03948eaf..17a7527f1a56 100644 --- a/gcc/testsuite/gcc.target/gcn/cond_umin_1_run.c +++ b/gcc/testsuite/gcc.target/gcn/cond_umin_1_run.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-require-effective-target vect_int } */ #include "cond_umin_1.c" diff --git a/gcc/testsuite/gcc.target/gcn/math-builtins-1.c b/gcc/testsuite/gcc.target/gcn/math-builtins-1.c index e1aadfb40d9f..e5fb3f5b990c 100644 --- a/gcc/testsuite/gcc.target/gcn/math-builtins-1.c +++ b/gcc/testsuite/gcc.target/gcn/math-builtins-1.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O1" } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ typedef float v64sf __attribute__ ((vector_size (256))); typedef double v64df __attribute__ ((vector_size (512))); diff --git a/gcc/testsuite/gcc.target/gcn/sgpr-spill-double.c b/gcc/testsuite/gcc.target/gcn/sgpr-spill-double.c index 910b4e650135..1915b0b1a79d 100644 --- a/gcc/testsuite/gcc.target/gcn/sgpr-spill-double.c +++ b/gcc/testsuite/gcc.target/gcn/sgpr-spill-double.c @@ -1,6 +1,11 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=gfx908 -O1" } */ +/* In SIMT mode every scalar becomes a 64-lane vector, so spills go to the + AVGPRs without ever using v_readlane (see simt-avgpr-spill-double.c); + the checks below only hold when building in SIMD mode. */ +/* { dg-require-effective-target amdgcn_simd } */ + /* Scalar values spilled out of VGPRs can be placed in either SGPRs or AVGPRs, so both may appear here; the array is large enough that both register files fill up and get used. */ diff --git a/gcc/testsuite/gcc.target/gcn/sgpr-spill-int.c b/gcc/testsuite/gcc.target/gcn/sgpr-spill-int.c index 536dba2544d5..a2182723902e 100644 --- a/gcc/testsuite/gcc.target/gcn/sgpr-spill-int.c +++ b/gcc/testsuite/gcc.target/gcn/sgpr-spill-int.c @@ -1,6 +1,11 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=gfx908 -O1" } */ +/* In SIMT mode every scalar becomes a 64-lane vector, so spills go to the + AVGPRs without ever using v_readlane (see simt-avgpr-spill-int.c); the + checks below only hold when building in SIMD mode. */ +/* { dg-require-effective-target amdgcn_simd } */ + /* Scalar values spilled out of VGPRs can be placed in either SGPRs or AVGPRs, so both may appear here; the array is large enough that both register files fill up and get used. */ diff --git a/gcc/testsuite/gcc.target/gcn/sgpr-spill-long.c b/gcc/testsuite/gcc.target/gcn/sgpr-spill-long.c index 57f6a7444ede..98fa958e48b3 100644 --- a/gcc/testsuite/gcc.target/gcn/sgpr-spill-long.c +++ b/gcc/testsuite/gcc.target/gcn/sgpr-spill-long.c @@ -1,6 +1,11 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=gfx908 -O1" } */ +/* In SIMT mode every scalar becomes a 64-lane vector, so spills go to the + AVGPRs without ever using v_readlane (see simt-avgpr-spill-long.c); the + checks below only hold when building in SIMD mode. */ +/* { dg-require-effective-target amdgcn_simd } */ + /* Scalar values spilled out of VGPRs can be placed in either SGPRs or AVGPRs, so both may appear here; the array is large enough that both register files fill up and get used. */ diff --git a/gcc/testsuite/gcc.target/gcn/sgpr-spill-short.c b/gcc/testsuite/gcc.target/gcn/sgpr-spill-short.c index f61a8eb58f98..76a84747224a 100644 --- a/gcc/testsuite/gcc.target/gcn/sgpr-spill-short.c +++ b/gcc/testsuite/gcc.target/gcn/sgpr-spill-short.c @@ -1,6 +1,11 @@ /* { dg-do compile } */ /* { dg-additional-options "-march=gfx908 -O1" } */ +/* In SIMT mode every scalar becomes a 64-lane vector, so spills go to the + AVGPRs without ever using v_readlane (see simt-avgpr-spill-short.c); the + checks below only hold when building in SIMD mode. */ +/* { dg-require-effective-target amdgcn_simd } */ + /* Scalar values spilled out of VGPRs can be placed in either SGPRs or AVGPRs, so both may appear here; the array is large enough that both register files fill up and get used. */ diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-1.c b/gcc/testsuite/gcc.target/gcn/simd-math-1.c index abd6a932a019..d738be363978 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-1.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-1.c @@ -4,6 +4,8 @@ /* { dg-options "-O2 -ftree-vectorize -fno-math-errno -mstack-size=3000000 -fdump-tree-vect" } */ /* The 'scan-tree-dump' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ #undef PRINT_RESULT #define VERBOSE 0 diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-2.c b/gcc/testsuite/gcc.target/gcn/simd-math-2.c index 375a2ad92631..bdd0657a244f 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-2.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-2.c @@ -3,6 +3,8 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize -fno-math-errno" } */ +/* { dg-require-effective-target vect_float } */ +/* { dg-require-effective-target vect_double } */ /* { dg-set-target-env-var "GCN_STACK_SIZE" "3000000" } */ #include "simd-math-1.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-16.c index 20fa12f0efc2..b7bbe089a93c 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-16.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-16.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define STYPE v16si #define UTYPE v16usi #define N 16 diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-2.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-2.c index 3baffe9ef011..d1424229a98c 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-2.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-2.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define STYPE v2si #define UTYPE v2usi #define N 2 diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-32.c index eab481584051..de25c7586cc3 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-32.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-32.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define STYPE v32si #define UTYPE v32usi #define N 32 diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-4.c index 370ca63554b1..4ed6850cd295 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-4.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-4.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define STYPE v4si #define UTYPE v4usi #define N 4 diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-8.c index 833608eaf2ae..db2d6a52dfa8 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-8.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-8.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define STYPE v8si #define UTYPE v8usi #define N 8 diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-16.c index f156d49cd2ab..55b5d3329b3f 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-16.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-16.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define STYPE v16qi #define UTYPE v16uqi #define N 16 diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-2.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-2.c index be4b9050fcde..5e6665b9fddc 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-2.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-2.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define STYPE v2qi #define UTYPE v2uqi #define N 2 diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-32.c index b0cadecb0d8e..9d99b9908a87 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-32.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-32.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define STYPE v32qi #define UTYPE v32uqi #define N 32 diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-4.c index 4dc7c783d358..95f3febd3455 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-4.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-4.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define STYPE v4qi #define UTYPE v4uqi #define N 4 diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-8.c index ea3753aaaf8f..822550def2cc 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-8.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-8.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define STYPE v8qi #define UTYPE v8uqi #define N 8 diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-16.c index 159b9802b073..bf8c49a3ed22 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-16.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-16.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-3-char-16.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-2.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-2.c index 6e730d07a038..b8ed022031f6 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-2.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-2.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-3-char-2.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-32.c index 8e4932bf5b97..b61b0a896a4e 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-32.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-32.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-3-char-32.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-4.c index d07a43183909..a0a8528d440e 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-4.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-4.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-3-char-4.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-8.c index 64f789a45286..e0978e1faa71 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-8.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run-8.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-3-char-8.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run.c index 4e2d4c0a19ab..22327d8e8c47 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char-run.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-3-char.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-char.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-char.c index 478d09e2ec7d..99742284708c 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-char.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-char.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define STYPE v64qi #define UTYPE v64uqi #include "simd-math-3.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-16.c index 530f29e37783..fd172320ea50 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-16.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-16.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define STYPE v16di #define UTYPE v16udi #define N 16 diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-2.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-2.c index 1c3e833c733b..0693f3133bec 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-2.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-2.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define STYPE v2di #define UTYPE v2udi #define N 2 diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-32.c index c8556a85ffd1..c30aa3c9db56 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-32.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-32.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define STYPE v32di #define UTYPE v32udi #define N 32 diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-4.c index 514396c565de..684f8df9a7d1 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-4.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-4.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define STYPE v4di #define UTYPE v4udi #define N 4 diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-8.c index 428e3a5a8078..fefc2c2d6b8e 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-8.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-8.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define STYPE v8di #define UTYPE v8udi #define N 8 diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-16.c index 7ce9c92a7a0e..2229a493be01 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-16.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-16.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-3-long-16.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-2.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-2.c index 20996a56f5c3..8c85a0b678e1 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-2.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-2.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-3-long-2.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-32.c index 1ca25ac9b511..2377af9a72ec 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-32.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-32.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-3-long-32.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-4.c index b31769ad0bc5..3009939215b9 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-4.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-4.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-3-long-4.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-8.c index 930256a0fc74..52869692348e 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-8.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run-8.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-3-long-8.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run.c index 363e42573d2d..47383e8e1a9d 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long-run.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-3-long.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-long.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-long.c index 321297b75bad..68d96aea111a 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-long.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-long.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define STYPE v64di #define UTYPE v64udi #include "simd-math-3.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-16.c index ae8cdbffa1d9..60e80096993e 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-16.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-16.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-3-16.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-2.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-2.c index 7d80382f23b7..c81ed35fc8ed 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-2.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-2.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-3-2.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-32.c index 127fd36f0f41..90cb14cca97b 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-32.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-32.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-3-32.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-4.c index e1d5b5de5c1d..e7fe27ac283f 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-4.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-4.c @@ -1,3 +1,4 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-3-4.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-8.c index ec98b60ae2ec..415f811eaa88 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-run-8.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-run-8.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-3-8.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-run.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-run.c index aca508cbc256..d05c0d12e3ca 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-run.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-run.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-3.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-16.c index 80f04149035a..9f9b85cbb3b6 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-16.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-16.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define STYPE v16hi #define UTYPE v16uhi #define N 16 diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-2.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-2.c index 37e5008a871e..8d31010ecd3d 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-2.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-2.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define STYPE v2hi #define UTYPE v2uhi #define N 2 diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-32.c index 79aada0ea5b3..f30a40cfa10a 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-32.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-32.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define STYPE v32hi #define UTYPE v32uhi #define N 32 diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-4.c index 014acacd2ea6..537862f2c7b0 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-4.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-4.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define STYPE v4hi #define UTYPE v4uhi #define N 4 diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-8.c index 308b72b53e24..5a74f5fbf0be 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-8.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-8.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define STYPE v8hi #define UTYPE v8uhi #define N 8 diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-16.c index 8ca866ce21ff..6a47c099760f 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-16.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-16.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-3-short-16.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-2.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-2.c index 6c6d8b68f28c..58ea6748f53a 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-2.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-2.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-3-short-2.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-32.c index 8c30ebc55280..bcc4d091e279 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-32.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-32.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-3-short-32.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-4.c index e70697e6e428..b089770f3d0d 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-4.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-4.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-3-short-4.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-8.c index 9cb9a6fe297b..de535791ccfc 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-8.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run-8.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-3-short-8.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run.c index 08f72671e96f..177a9c61264b 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short-run.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-3-short.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3-short.c b/gcc/testsuite/gcc.target/gcn/simd-math-3-short.c index 1ade288f3896..37a1ae30b3ab 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3-short.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3-short.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define STYPE v64hi #define UTYPE v64uhi #include "simd-math-3.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-3.c b/gcc/testsuite/gcc.target/gcn/simd-math-3.c index def838524617..5604a6fb5dac 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-3.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-3.c @@ -1,6 +1,8 @@ /* Test that signed and unsigned division and modulus use the correct vector routines and give the correct results. */ +/* { dg-require-effective-target vect_int } */ + /* Setting it this way ensures the run tests use the same flag as the compile tests. */ #pragma GCC optimize("O2") diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-4-char-run.c b/gcc/testsuite/gcc.target/gcn/simd-math-4-char-run.c index b328a3eeec5c..db349e976446 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-4-char-run.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-4-char-run.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-4-char.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-4-char.c b/gcc/testsuite/gcc.target/gcn/simd-math-4-char.c index df24bd4e56d8..255a76245011 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-4-char.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-4-char.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define TYPE v64qi #include "simd-math-4.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-4-long-run.c b/gcc/testsuite/gcc.target/gcn/simd-math-4-long-run.c index 34cbc467709e..ba84a89435f3 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-4-long-run.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-4-long-run.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-4-long.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-4-long.c b/gcc/testsuite/gcc.target/gcn/simd-math-4-long.c index 768a0dfc848c..0730cafb9eaf 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-4-long.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-4-long.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define TYPE v64di #include "simd-math-4.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-4-run.c b/gcc/testsuite/gcc.target/gcn/simd-math-4-run.c index 3b98c0e77387..7a818babc710 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-4-run.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-4-run.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-4.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-4-short-run.c b/gcc/testsuite/gcc.target/gcn/simd-math-4-short-run.c index 4cbeb97432e2..b16ce27b5a39 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-4-short-run.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-4-short-run.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-4-short.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-4-short.c b/gcc/testsuite/gcc.target/gcn/simd-math-4-short.c index f010942ffad5..0c7fee1aaa96 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-4-short.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-4-short.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define TYPE v64hi #include "simd-math-4.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-4.c index 833dfe2a8667..bbb723fcaa68 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-4.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-4.c @@ -1,6 +1,8 @@ /* Test that signed division and modulus give the correct result with different variations of signedness. */ +/* { dg-require-effective-target vect_int } */ + /* Setting it this way ensures the run tests use the same flag as the compile tests. */ #pragma GCC optimize("O2") diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-16.c index 41c116758b41..a30fc48612ba 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-16.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-16.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define N 16 #include "simd-math-5.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-32.c index 3fb92b2aab28..f67f29a951cb 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-32.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-32.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define N 32 #include "simd-math-5.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-4.c index ffcd51201789..046b723c97f9 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-4.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-4.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define N 4 #include "simd-math-5.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-8.c index 5d855b627522..7fe53032afec 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-8.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-8.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define N 8 #include "simd-math-5.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-16.c index 0ebf640dc8cc..6c358dc27df9 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-16.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-16.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define TYPE char #define N 16 #include "simd-math-5.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-32.c index 0905f31048c2..e1675964a769 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-32.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-32.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define TYPE char #define N 32 #include "simd-math-5.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-4.c index 772fe37fe810..3bfd44ae8375 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-4.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-4.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define TYPE char #define N 4 #include "simd-math-5.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-8.c index 539ce9a7f912..fe612ccfe1b9 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-8.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-8.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define TYPE char #define N 8 #include "simd-math-5.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-16.c index 0f1af0858ca0..5d3390fb9726 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-16.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-16.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-5-char-16.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-32.c index a2794c84a839..cbcd184d7bf6 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-32.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-32.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-5-char-32.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-4.c index a8e418770ff2..ce752f846dbe 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-4.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-4.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-5-char-4.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-8.c index 7a6a95922cc1..138bd1baec7a 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-8.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run-8.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-5-char-8.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run.c index d3ca775f6a92..3cb1f3671fdd 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char-run.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-5-char.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-char.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-char.c index e3521ce7ca31..edcb4e370995 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-char.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-char.c @@ -1,5 +1,6 @@ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_int } */ #define TYPE char #include "simd-math-5.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-16.c index 659907d8d525..7ec7eebb2746 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-16.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-16.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define TYPE long #define N 16 #include "simd-math-5.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-32.c index b03fd0924707..c3cbdf74055f 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-32.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-32.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define TYPE long #define N 32 #include "simd-math-5.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-4.c index a8877b6c63b9..0b848cc2013b 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-4.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-4.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define TYPE long #define N 4 #include "simd-math-5.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-8.c index 5b1106c73aff..612d7e7105e3 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-8.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-8.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define TYPE long #define N 8 #include "simd-math-5.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-16.c index 209192554045..1c4ef965324a 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-16.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-16.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-5-long-16.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-32.c index c7ff7ca52b9f..ed1947422439 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-32.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-32.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-5-long-32.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-4.c index c6cf3344ec46..25179ca8d2b2 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-4.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-4.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-5-long-4.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-8.c index 85fdf6ffe1b0..128a8d5a4ea7 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-8.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run-8.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-5-long-8.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run.c index b948fa08c7e8..679b9bfa3c97 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long-run.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-5-long.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-long.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-long.c index 96a9fd3e734e..a7a0e0d91b5f 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-long.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-long.c @@ -1,5 +1,6 @@ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_int } */ #define TYPE long #include "simd-math-5.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-run-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-run-16.c index 209192554045..1c4ef965324a 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-run-16.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-run-16.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-5-long-16.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-run-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-run-32.c index c7ff7ca52b9f..ed1947422439 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-run-32.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-run-32.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-5-long-32.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-run-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-run-4.c index c6cf3344ec46..25179ca8d2b2 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-run-4.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-run-4.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-5-long-4.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-run-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-run-8.c index 85fdf6ffe1b0..128a8d5a4ea7 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-run-8.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-run-8.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-5-long-8.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-run.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-run.c index de6504c737c3..3ea40b3d2e91 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-run.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-run.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-5.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-16.c index 5d5953bc604e..345cff8949af 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-16.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-16.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define TYPE short #define N 16 #include "simd-math-5.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-32.c index bf8a3addfc49..91147b29ba28 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-32.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-32.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define TYPE short #define N 32 #include "simd-math-5.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-4.c index a2cb46c8646f..65701710605f 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-4.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-4.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define TYPE short #define N 4 #include "simd-math-5.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-8.c index fa343e5262eb..1dcbf76294db 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-8.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-8.c @@ -1,3 +1,4 @@ +/* { dg-require-effective-target vect_int } */ #define TYPE short #define N 8 #include "simd-math-5.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-16.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-16.c index 3fc946e2e09c..5e314b4b7cdd 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-16.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-16.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-5-short-16.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-32.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-32.c index 34b1d75fa8eb..20cc263a7ad2 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-32.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-32.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-5-short-32.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-4.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-4.c index 09385c78bc4f..612160dd70ec 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-4.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-4.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-5-short-4.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-8.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-8.c index 1de4d2631b32..ccd1b8514765 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-8.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run-8.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-5-short-8.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run.c index 2e0c490fdd91..72dbbea78ee2 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short-run.c @@ -1,2 +1,3 @@ /* { dg-do run } */ +/* { dg-require-effective-target vect_int } */ #include "simd-math-5-short.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5-short.c b/gcc/testsuite/gcc.target/gcn/simd-math-5-short.c index c0bff40380a3..3a8fadc9ee7f 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5-short.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5-short.c @@ -1,5 +1,6 @@ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_int } */ #define TYPE short #include "simd-math-5.c" diff --git a/gcc/testsuite/gcc.target/gcn/simd-math-5.c b/gcc/testsuite/gcc.target/gcn/simd-math-5.c index b5c5dc9f288e..2316a89ef905 100644 --- a/gcc/testsuite/gcc.target/gcn/simd-math-5.c +++ b/gcc/testsuite/gcc.target/gcn/simd-math-5.c @@ -3,6 +3,7 @@ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_int } */ /* Setting it this way ensures the run tests use the same flag as the compile tests. */ diff --git a/gcc/testsuite/gcc.target/gcn/smax_1.c b/gcc/testsuite/gcc.target/gcn/smax_1.c index eec050caf711..9f4d76b6c008 100644 --- a/gcc/testsuite/gcc.target/gcn/smax_1.c +++ b/gcc/testsuite/gcc.target/gcn/smax_1.c @@ -2,6 +2,7 @@ /* { dg-options "-O2 -ftree-vectorize -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_int } */ #include <stdint.h> diff --git a/gcc/testsuite/gcc.target/gcn/smax_1_run.c b/gcc/testsuite/gcc.target/gcn/smax_1_run.c index 4f9759162297..1181c0fc96eb 100644 --- a/gcc/testsuite/gcc.target/gcn/smax_1_run.c +++ b/gcc/testsuite/gcc.target/gcn/smax_1_run.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-require-effective-target vect_int } */ #include "smax_1.c" diff --git a/gcc/testsuite/gcc.target/gcn/smin_1.c b/gcc/testsuite/gcc.target/gcn/smin_1.c index 8aa8cbb9db88..f8423ffeff90 100644 --- a/gcc/testsuite/gcc.target/gcn/smin_1.c +++ b/gcc/testsuite/gcc.target/gcn/smin_1.c @@ -2,6 +2,7 @@ /* { dg-options "-O2 -ftree-vectorize -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_int } */ #include <stdint.h> diff --git a/gcc/testsuite/gcc.target/gcn/smin_1_run.c b/gcc/testsuite/gcc.target/gcn/smin_1_run.c index 6758d571fe2e..29071834c899 100644 --- a/gcc/testsuite/gcc.target/gcn/smin_1_run.c +++ b/gcc/testsuite/gcc.target/gcn/smin_1_run.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-require-effective-target vect_int } */ #include "smin_1.c" diff --git a/gcc/testsuite/gcc.target/gcn/sram-ecc-3.c b/gcc/testsuite/gcc.target/gcn/sram-ecc-3.c index bc89e3542d2d..da5405537cb3 100644 --- a/gcc/testsuite/gcc.target/gcn/sram-ecc-3.c +++ b/gcc/testsuite/gcc.target/gcn/sram-ecc-3.c @@ -4,6 +4,7 @@ /* { dg-do compile } */ /* { dg-options "-O2 -ftree-vectorize -dp -msram-ecc=off" } */ +/* { dg-require-effective-target vect_int } */ typedef unsigned int v64si __attribute__ ((vector_size (64*4))); typedef unsigned char v64qi __attribute__ ((vector_size (64*1))); diff --git a/gcc/testsuite/gcc.target/gcn/sram-ecc-4.c b/gcc/testsuite/gcc.target/gcn/sram-ecc-4.c index ff7e2d0bda52..8b509fbfce29 100644 --- a/gcc/testsuite/gcc.target/gcn/sram-ecc-4.c +++ b/gcc/testsuite/gcc.target/gcn/sram-ecc-4.c @@ -4,6 +4,7 @@ /* { dg-do compile } */ /* { dg-options "-O2 -ftree-vectorize -dp -msram-ecc=off" } */ +/* { dg-require-effective-target vect_int } */ typedef unsigned int v64si __attribute__ ((vector_size (64*4))); typedef unsigned short v64hi __attribute__ ((vector_size (64*2))); diff --git a/gcc/testsuite/gcc.target/gcn/sram-ecc-7.c b/gcc/testsuite/gcc.target/gcn/sram-ecc-7.c index 8d363970ffb7..426f5c0e55a4 100644 --- a/gcc/testsuite/gcc.target/gcn/sram-ecc-7.c +++ b/gcc/testsuite/gcc.target/gcn/sram-ecc-7.c @@ -4,6 +4,7 @@ /* { dg-do compile } */ /* { dg-options "-O2 -ftree-vectorize -dp -msram-ecc=any" } */ +/* { dg-require-effective-target vect_int } */ typedef unsigned int v64si __attribute__ ((vector_size (64*4))); typedef unsigned char v64qi __attribute__ ((vector_size (64*1))); diff --git a/gcc/testsuite/gcc.target/gcn/sram-ecc-8.c b/gcc/testsuite/gcc.target/gcn/sram-ecc-8.c index a2b25076ed1d..23d1c7d1161b 100644 --- a/gcc/testsuite/gcc.target/gcn/sram-ecc-8.c +++ b/gcc/testsuite/gcc.target/gcn/sram-ecc-8.c @@ -4,6 +4,7 @@ /* { dg-do compile } */ /* { dg-options "-O2 -ftree-vectorize -dp -msram-ecc=any" } */ +/* { dg-require-effective-target vect_int } */ typedef unsigned int v64si __attribute__ ((vector_size (64*4))); typedef unsigned short v64hi __attribute__ ((vector_size (64*2))); diff --git a/gcc/testsuite/gcc.target/gcn/umax_1.c b/gcc/testsuite/gcc.target/gcn/umax_1.c index 934bf9a4a7cb..48d2cec01504 100644 --- a/gcc/testsuite/gcc.target/gcn/umax_1.c +++ b/gcc/testsuite/gcc.target/gcn/umax_1.c @@ -2,6 +2,7 @@ /* { dg-options "-O2 -ftree-vectorize -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_int } */ #include <stdint.h> diff --git a/gcc/testsuite/gcc.target/gcn/umax_1_run.c b/gcc/testsuite/gcc.target/gcn/umax_1_run.c index b8ff54044fd4..7e5e644eae1b 100644 --- a/gcc/testsuite/gcc.target/gcn/umax_1_run.c +++ b/gcc/testsuite/gcc.target/gcn/umax_1_run.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-require-effective-target vect_int } */ #include "umax_1.c" diff --git a/gcc/testsuite/gcc.target/gcn/umin_1.c b/gcc/testsuite/gcc.target/gcn/umin_1.c index 44343bd44cf9..78a28e4b391c 100644 --- a/gcc/testsuite/gcc.target/gcn/umin_1.c +++ b/gcc/testsuite/gcc.target/gcn/umin_1.c @@ -2,6 +2,7 @@ /* { dg-options "-O2 -ftree-vectorize -dp" } */ /* The 'scan-assembler' directives are specific to 64-lane vectors. { dg-additional-options --param=gcn-preferred-vectorization-factor=64 } */ +/* { dg-require-effective-target vect_int } */ #include <stdint.h> diff --git a/gcc/testsuite/gcc.target/gcn/umin_1_run.c b/gcc/testsuite/gcc.target/gcn/umin_1_run.c index a15d7b3982ac..7c40422d89a8 100644 --- a/gcc/testsuite/gcc.target/gcn/umin_1_run.c +++ b/gcc/testsuite/gcc.target/gcn/umin_1_run.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2 -ftree-vectorize" } */ +/* { dg-require-effective-target vect_int } */ #include "umin_1.c" diff --git a/gcc/testsuite/gcc.target/gcn/vcc-clobber.c b/gcc/testsuite/gcc.target/gcn/vcc-clobber.c index e52733cf1e54..df8b6721078c 100644 --- a/gcc/testsuite/gcc.target/gcn/vcc-clobber.c +++ b/gcc/testsuite/gcc.target/gcn/vcc-clobber.c @@ -1,5 +1,6 @@ /* { dg-do run } */ /* { dg-options "-O2" } */ +/* { dg-require-effective-target vect_int } */ /* Test that gcn_expand_scalar_to_vector_address does not clobber VCC. If it does then spills and reloads will be unsafe, leading to unexpected diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 2bf9d868bfc8..b1c01a62f484 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -4653,7 +4653,7 @@ proc check_effective_target_vect_int { } { expr { [check_effective_target_x86] || [istarget powerpc*-*-*] - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || [istarget sparc*-*-*] || [istarget alpha*-*-*] || [istarget ia64-*-*] @@ -4696,7 +4696,7 @@ proc check_effective_target_vect_early_break { } { [istarget aarch64*-*-*] || [check_effective_target_arm_v8_neon_ok] || [check_effective_target_sse4] - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || [check_effective_target_riscv_v] || [check_effective_target_loongarch_sx] }}] @@ -4713,7 +4713,7 @@ proc check_effective_target_vect_early_break_hw { } { [istarget aarch64*-*-*] || [check_effective_target_arm_v8_neon_hw] || [check_sse4_hw_available] - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || [check_effective_target_riscv_v_ok] || [check_effective_target_loongarch_sx_hw] }}] @@ -4857,7 +4857,7 @@ proc check_effective_target_vect_intfloat_cvt { } { || [is-effective-target arm_neon] || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || ([istarget s390*-*-*] && [check_effective_target_s390_vxe2]) || ([istarget riscv*-*-*] @@ -4937,7 +4937,7 @@ proc check_effective_target_vect_uintfloat_cvt { } { || [is-effective-target arm_neon] || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || ([istarget s390*-*-*] && [check_effective_target_s390_vxe2]) || ([istarget riscv*-*-*] @@ -4957,7 +4957,7 @@ proc check_effective_target_vect_floatint_cvt { } { || [is-effective-target arm_neon] || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || ([istarget s390*-*-*] && [check_effective_target_s390_vxe2]) || ([istarget riscv*-*-*] @@ -4975,7 +4975,7 @@ proc check_effective_target_vect_floatuint_cvt { } { || [is-effective-target arm_neon] || ([istarget mips*-*-*] && [et-is-effective-target mips_msa]) - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || ([istarget s390*-*-*] && [check_effective_target_s390_vxe2]) || ([istarget riscv*-*-*] @@ -5017,7 +5017,7 @@ proc check_effective_target_vect_simd_clones { } { return [check_cached_effective_target vect_simd_clones { expr { ([check_effective_target_x86] && [check_effective_target_avx512f]) - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || [istarget aarch64*-*-*] }}] } @@ -8418,7 +8418,7 @@ proc check_effective_target_vect_shift { } { || [et-is-effective-target mips_loongson_mmi])) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) || ([istarget loongarch*-*-*] @@ -8450,7 +8450,7 @@ proc check_effective_target_whole_vector_shift { } { && [et-is-effective-target mips_loongson_mmi]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) || ([istarget loongarch*-*-*] @@ -8470,7 +8470,7 @@ proc check_effective_target_vect_bswap { } { return [check_cached_effective_target vect_bswap { expr { ([istarget aarch64*-*-*] || [is-effective-target arm_neon] - || [istarget amdgcn-*-*]) + || [check_effective_target_amdgcn_simd]) || [istarget loongarch*-*-*] || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) }}] @@ -8498,7 +8498,7 @@ proc check_effective_target_vect_char_add { } { expr { [check_effective_target_x86] || [istarget powerpc*-*-*] - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || [istarget ia64-*-*] || [istarget aarch64*-*-*] || [is-effective-target arm_neon] @@ -8524,7 +8524,7 @@ proc check_effective_target_vect_shift_char { } { && [et-is-effective-target mips_msa]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) || ([istarget loongarch*-*-*] @@ -8546,7 +8546,7 @@ proc check_effective_target_vect_long { } { && [et-is-effective-target mips_msa]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) || ([istarget loongarch*-*-*] @@ -8578,7 +8578,7 @@ proc check_effective_target_vect_float { } { || [is-effective-target arm_neon] || ([istarget s390*-*-*] && [check_effective_target_s390_vxe]) - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) || ([istarget loongarch*-*-*] @@ -8611,7 +8611,7 @@ proc check_effective_target_vect_double { } { && [et-is-effective-target mips_msa]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) || ([istarget loongarch*-*-*] @@ -8645,7 +8645,7 @@ proc check_effective_target_vect_long_long { } { && [check_effective_target_riscv_v]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) - || [istarget amdgcn-*-*] }}] + || [check_effective_target_amdgcn_simd] }}] } @@ -8698,7 +8698,7 @@ proc check_effective_target_vect_perm { } { || [et-is-effective-target mips_msa])) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) || ([istarget loongarch*-*-*] @@ -8795,7 +8795,7 @@ proc check_effective_target_vect_perm_byte { } { && [et-is-effective-target mips_msa]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) || ([istarget loongarch*-*-*] @@ -8828,7 +8828,7 @@ proc check_effective_target_vect_perm_short { } { && [et-is-effective-target mips_msa]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) || ([istarget loongarch*-*-*] @@ -8954,7 +8954,7 @@ proc check_effective_target_vect_widen_mult_qi_to_hi { } { || [is-effective-target arm_neon] || ([istarget s390*-*-*] && [check_effective_target_s390_vx])) - || [istarget amdgcn-*-*] }}] + || [check_effective_target_amdgcn_simd] }}] } # Return 1 if the target plus current options supports a vector @@ -8978,7 +8978,7 @@ proc check_effective_target_vect_widen_mult_hi_to_si { } { || [is-effective-target arm_neon] || ([istarget s390*-*-*] && [check_effective_target_s390_vx])) - || [istarget amdgcn-*-*] }}] + || [check_effective_target_amdgcn_simd] }}] } # Return 1 if the target plus current options supports a vector @@ -8994,7 +8994,7 @@ proc check_effective_target_vect_widen_mult_qi_to_hi_pattern { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) || [istarget loongarch*-*-*] - || [istarget amdgcn-*-*] }}] + || [check_effective_target_amdgcn_simd] }}] } # Return 1 if the target plus current options supports a vector @@ -9012,7 +9012,7 @@ proc check_effective_target_vect_widen_mult_hi_to_si_pattern { } { && [check_effective_target_arm_little_endian]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] }}] + || [check_effective_target_amdgcn_simd] }}] } # Return 1 if the target plus current options supports a vector @@ -9187,7 +9187,7 @@ proc check_effective_target_vect_pack_trunc { } { && [et-is-effective-target mips_msa]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn*-*-*] + || [check_effective_target_amdgcn_simd] || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) || ([istarget loongarch*-*-*] @@ -9211,7 +9211,7 @@ proc check_effective_target_vect_unpack { } { && [check_effective_target_arm_little_endian]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn*-*-*] + || [check_effective_target_amdgcn_simd] || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) || ([istarget loongarch*-*-*] @@ -9257,7 +9257,7 @@ proc check_effective_target_vect_hw_misalign { } { || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) || ([istarget loongarch*-*-*]) - || [istarget amdgcn*-*-*] } { + || [check_effective_target_amdgcn_simd] } { return 1 } if { [istarget arm*-*-*] @@ -9349,7 +9349,7 @@ proc check_effective_target_vect_natural_alignment { } { if { [check_effective_target_arm_eabi] || [istarget nvptx-*-*] || [istarget s390*-*-*] - || [istarget amdgcn-*-*] } { + || [check_effective_target_amdgcn_simd] } { set et_vect_natural_alignment 0 } verbose "check_effective_target_vect_natural_alignment:\ @@ -9368,7 +9368,7 @@ proc check_effective_target_vect_check_ptrs { } { proc check_effective_target_vect_fully_masked { } { return [expr { [check_effective_target_aarch64_sve] - || [istarget amdgcn*-*-*] + || [check_effective_target_amdgcn_simd] || [check_effective_target_riscv_v] }] } @@ -9854,7 +9854,7 @@ proc check_effective_target_vect_load_lanes { } { proc check_effective_target_vect_masked_load { } { return [expr { [check_avx_available] || [check_effective_target_aarch64_sve] - || [istarget amdgcn*-*-*] + || [check_effective_target_amdgcn_simd] || [check_effective_target_riscv_v] } ] } @@ -9863,7 +9863,7 @@ proc check_effective_target_vect_masked_load { } { proc check_effective_target_vect_masked_store { } { return [expr { [check_avx_available] || [check_effective_target_aarch64_sve] - || [istarget amdgcn*-*-*] + || [check_effective_target_amdgcn_simd] || [check_effective_target_riscv_v] }] } @@ -9871,7 +9871,7 @@ proc check_effective_target_vect_masked_store { } { proc check_effective_target_vect_gather_load_ifn { } { return [expr { [check_effective_target_aarch64_sve] - || [istarget amdgcn*-*-*] + || [check_effective_target_amdgcn_simd] || [check_effective_target_riscv_v] }] } @@ -9879,7 +9879,7 @@ proc check_effective_target_vect_gather_load_ifn { } { proc check_effective_target_vect_scatter_store { } { return [expr { [check_effective_target_aarch64_sve] - || [istarget amdgcn*-*-*] + || [check_effective_target_amdgcn_simd] || [check_effective_target_riscv_v] || [check_effective_target_loongarch_sx] }] } @@ -9897,7 +9897,7 @@ proc check_effective_target_vect_condition { } { || [check_effective_target_arm_neon_ok] || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) || ([istarget loongarch*-*-*] @@ -9917,7 +9917,7 @@ proc check_effective_target_vect_cond_mixed { } { && [et-is-effective-target mips_msa]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) || ([istarget loongarch*-*-*] @@ -9937,7 +9937,7 @@ proc check_effective_target_vect_char_mult { } { && [et-is-effective-target mips_msa]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) || ([istarget loongarch*-*-*] @@ -9958,7 +9958,7 @@ proc check_effective_target_vect_short_mult { } { || [et-is-effective-target mips_loongson_mmi])) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) || ([istarget loongarch*-*-*] @@ -9978,7 +9978,7 @@ proc check_effective_target_vect_int_mult { } { || [check_effective_target_arm32] || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) || ([istarget loongarch*-*-*] @@ -10007,7 +10007,7 @@ proc check_effective_target_vect_long_mult { } { && [check_effective_target_riscv_v]) || ([istarget loongarch*-*-*] && [check_effective_target_loongarch_sx]) - || [istarget amdgcn-*-*] } { + || [check_effective_target_amdgcn_simd] } { set answer 1 } else { set answer 0 @@ -10176,7 +10176,7 @@ proc check_effective_target_vect_call_copysignf { } { expr { [check_effective_target_x86] || [istarget powerpc*-*-*] || [istarget aarch64*-*-*] - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) || ([istarget loongarch*-*-*] @@ -10217,7 +10217,7 @@ proc check_effective_target_vect_call_sqrtf { } { || ([istarget powerpc*-*-*] && [check_vsx_hw_available]) || ([istarget s390*-*-*] && [check_effective_target_s390_vx]) - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || ([istarget riscv*-*-*] && [check_effective_target_riscv_v]) || ([istarget loongarch*-*-*] @@ -10230,7 +10230,7 @@ proc check_effective_target_vect_call_lrint { } { set et_vect_call_lrint 0 if { ([check_effective_target_x86] && [check_effective_target_ilp32]) - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || [istarget loongarch*-*-*] } { set et_vect_call_lrint 1 } @@ -10244,7 +10244,7 @@ proc check_effective_target_vect_call_lrint { } { proc check_effective_target_vect_call_btrunc { } { return [check_cached_effective_target vect_call_btrunc { expr { [istarget aarch64*-*-*] - || [istarget amdgcn-*-*] }}] + || [check_effective_target_amdgcn_simd] }}] } # Return 1 if the target supports vector btruncf calls. @@ -10252,7 +10252,7 @@ proc check_effective_target_vect_call_btrunc { } { proc check_effective_target_vect_call_btruncf { } { return [check_cached_effective_target vect_call_btruncf { expr { [istarget aarch64*-*-*] - || [istarget amdgcn-*-*] }}] + || [check_effective_target_amdgcn_simd] }}] } # Return 1 if the target supports vector ceil calls. @@ -10260,7 +10260,7 @@ proc check_effective_target_vect_call_btruncf { } { proc check_effective_target_vect_call_ceil { } { return [check_cached_effective_target vect_call_ceil { expr { [istarget aarch64*-*-*] - || [istarget amdgcn-*-*] }}] + || [check_effective_target_amdgcn_simd] }}] } # Return 1 if the target supports vector ceilf calls. @@ -10268,7 +10268,7 @@ proc check_effective_target_vect_call_ceil { } { proc check_effective_target_vect_call_ceilf { } { return [check_cached_effective_target vect_call_ceilf { expr { [istarget aarch64*-*-*] - || [istarget amdgcn-*-*] }}] + || [check_effective_target_amdgcn_simd] }}] } # Return 1 if the target supports vector floor calls. @@ -10276,7 +10276,7 @@ proc check_effective_target_vect_call_ceilf { } { proc check_effective_target_vect_call_floor { } { return [check_cached_effective_target vect_call_floor { expr { [istarget aarch64*-*-*] - || [istarget amdgcn-*-*] }}] + || [check_effective_target_amdgcn_simd] }}] } # Return 1 if the target supports vector floorf calls. @@ -10284,7 +10284,7 @@ proc check_effective_target_vect_call_floor { } { proc check_effective_target_vect_call_floorf { } { return [check_cached_effective_target vect_call_floorf { expr { [istarget aarch64*-*-*] - || [istarget amdgcn-*-*] }}] + || [check_effective_target_amdgcn_simd] }}] } # Return 1 if the target supports vector lceil calls. @@ -10333,7 +10333,7 @@ proc check_effective_target_vect_call_roundf { } { proc check_effective_target_vect_logical_reduc { } { return [expr { [check_effective_target_aarch64_sve] - || [istarget amdgcn-*-*] + || [check_effective_target_amdgcn_simd] || [check_effective_target_riscv_v] || [check_effective_target_loongarch_sx] || [check_effective_target_x86] @@ -10344,7 +10344,7 @@ proc check_effective_target_vect_logical_reduc { } { proc check_effective_target_vect_fold_extract_last { } { return [expr { [check_effective_target_aarch64_sve] - || [istarget amdgcn*-*-*] + || [check_effective_target_amdgcn_simd] || [check_effective_target_riscv_v] }] } @@ -12760,6 +12760,9 @@ proc check_vect_support_and_set_flags { } { set dg-do-what-default compile } } elseif [istarget amdgcn-*-*] { + if { ![check_effective_target_amdgcn_simd] } { + return 0 + } set dg-do-what-default run } elseif [istarget riscv*-*-*] { if [check_effective_target_riscv_v] { @@ -15093,3 +15096,31 @@ proc check_effective_target_can_deref_null { } { } } "-O0 -fno-delete-null-pointer-checks -Wno-null-dereference"] } + +# Return 1 if the target is amdgcn and is building in SIMD mode. +# The vector modes only exist in SIMD mode, so the vect_* effective targets +# use this to decide whether amdgcn has vectors at all. + +proc check_effective_target_amdgcn_simd { } { + if { ![istarget amdgcn-*-*] } { + return 0 + } + return [check_no_compiler_messages amdgcn_simd_ assembly { + #ifdef __SIMT__ + #error "not simd" + #endif + }] +} + +# Return 1 if the target is amdgcn and is building in SIMT mode + +proc check_effective_target_amdgcn_simt { } { + if { ![istarget amdgcn-*-*] } { + return 0 + } + return [check_no_compiler_messages amdgcn_simt_ assembly { + #ifndef __SIMT__ + #error "not simt" + #endif + }] +}
