https://gcc.gnu.org/g:f8d28739227adabf200b674c22a35599fe87b53d
commit r17-5463-gf8d28739227adabf200b674c22a35599fe87b53d Author: Jeff Law <[email protected]> Date: Wed Oct 21 08:47:16 2026 -0600 [RISC-V] Fix invalid accessor macro use in RISC-V bitmanip support A few more bitmanip.md fixes for LLM exposed issues. This patch targets the potential to use an accessor like [U]INTVAL on something that is not a CONST_INT. The common case is accepting an immediate_operand, then checking [U]INTVAL in the insn's condition. So if the pattern were passed a CONST node we could either get unexpected results or an ICE. So instead of immediate_operand, we can use the tighter const_int_operand. There's a similar kind of case with arith_operand accepting REGs, so requesting UINTVAL is just bogus. There was one case of potentially letting a SUBREG through and testing its REGNO. This was actually fixed up in the predicate. Given how obviously wrong these cases were, I didn't ask the LLM to try and generate tests. Ideally we squash these out and going forward review catches them before they get into the tree. Bootstrapped and regression tested on the k3, c920 and k1. Also tested on riscv64-elf and riscv32-elf. Pushing to the trunk. gcc/ * config/riscv/bitmanip.md (shNadduw): Use const_int_operand rather than immediate_operand and const_arith_oprerand instead of arith_operand. (slliuw, bexti): Similarly. (bclr splitter with masked position): Similarly. * config/riscv/predicates.md (x1x5_operand): Only allow REGs. Diff: --- gcc/config/riscv/bitmanip.md | 10 +++++----- gcc/config/riscv/predicates.md | 1 + 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 1027aa2dc066..b35743d7f361 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -115,7 +115,7 @@ (plus:DI (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") (match_operand:QI 2 "imm123_operand" "Ds3")) - (match_operand 3 "immediate_operand" "n")) + (match_operand 3 "const_int_operand" "n")) (match_operand:DI 4 "register_operand" "r")))] "TARGET_64BIT && TARGET_ZBA && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff" @@ -233,8 +233,8 @@ (define_insn "riscv_slli_uw" [(set (match_operand:DI 0 "register_operand" "=r") (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") - (match_operand:QI 2 "immediate_operand" "I")) - (match_operand 3 "immediate_operand" "n")))] + (match_operand:QI 2 "const_int_operand" "I")) + (match_operand 3 "const_int_operand" "n")))] "TARGET_64BIT && TARGET_ZBA && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff" "slli.uw\t%0,%1,%2" @@ -1008,7 +1008,7 @@ (and:DI (not:DI (subreg:DI (ashift:SI (const_int 1) (match_operand:QI 1 "register_operand")) 0)) - (match_operand:DI 2 "arith_operand"))) + (match_operand:DI 2 "const_arith_operand"))) (clobber (match_operand:DI 3 "register_operand"))] "TARGET_64BIT && TARGET_ZBS && clz_hwi (INTVAL (operands[2])) >= 33" @@ -1117,7 +1117,7 @@ [(set (match_operand:X 0 "register_operand" "=r") (zero_extract:X (match_operand:X 1 "register_operand" "r") (const_int 1) - (match_operand 2 "immediate_operand" "n")))] + (match_operand 2 "const_int_operand" "n")))] "TARGET_ZBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)" "bexti\t%0,%1,%2" [(set_attr "type" "bitmanip")]) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 17ca8ef093a6..f019426007cb 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -742,6 +742,7 @@ ;; Shadow stack operands only allow x1, x5 registers (define_predicate "x1x5_operand" (and (match_operand 0 "register_operand") + (match_test "GET_CODE (op) == REG") (match_test "REGNO (op) == RETURN_ADDR_REGNUM || REGNO (op) == T0_REGNUM")))
