https://gcc.gnu.org/g:83672fad13bb8789d742046bc1f37ad8f06a9fda
commit r17-5526-g83672fad13bb8789d742046bc1f37ad8f06a9fda Author: Pan Li <[email protected]> Date: Tue Sep 29 11:50:51 2026 +0800 RISC-V: Allow RVV register overlap for vfwsub.wv Like vfwadd.wv, allow the rvv register overlap for the vfwsub.wv, aka 2 * SEW = 2 * SEW - SEW form. 1. The vs1 can overlap to the highest part of the vd. 2. The vs1 cannot overlap the group of vs2. gcc/ChangeLog: * config/riscv/vector.md: Take the Wn4 constraint for the operand 3 and the Wvr constraint for the operand 4 of the vfwsub.wv. Signed-off-by: Pan Li <[email protected]> Diff: --- gcc/config/riscv/vector.md | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index b994125fe088..6b82620c61f4 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7370,23 +7370,23 @@ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "@pred_single_widen_sub<mode>" - [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr") + [(set (match_operand:VWEXTF 0 "register_operand" "=vr, vr, vd, vd") (if_then_else:VWEXTF (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rvl, rvl") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (match_operand 9 "const_int_operand" " i, i") + [(match_operand:<VM> 1 "vector_mask_operand" "Wc1,Wc1, vm, vm") + (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (minus:VWEXTF - (match_operand:VWEXTF 3 "register_operand" " vr, vr") + (match_operand:VWEXTF 3 "register_operand" "Wn4,Wn4,Wn4,Wn4") (float_extend:VWEXTF - (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr"))) - (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))] + (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "Wvr,Wvr,Wvr,Wvr"))) + (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vfwsub.wv\t%0,%3,%4%p1" [(set_attr "type" "vfwalu")
