https://gcc.gnu.org/g:cada5a5bcdc4ec5e1d8e56fed922330e8b95887c
commit r17-5541-gcada5a5bcdc4ec5e1d8e56fed922330e8b95887c Author: Jeff Law <[email protected]> Date: Sat Oct 24 10:28:13 2026 -0600 [RISC-V] Fix incorrect long branch sequence for Andes and REGNO reference in peephole More LLM discovered issues. First in andes.md we're trying to emit a conditional branch around a long branch sequence. That's usually done by using a forward label like 0f or 1f. The output template used %1f, so it's going to append 'f' to whatever the output string is for operand1. Opps. That output template should just use 1f. There's other problems with the long branch sequences, but I need to read the Andes manual to make sure I don't muck up the fix. Second was a case where we're using REGNO on an object that could be a SUBREG. It's a pretty low impact peephole, so I've just adjusted the condition to ensure the operands are REGs. Tested on riscv64-elf and riscv32-elf. However, I doubt that really exercises either of these two paths at all. gcc/ * config/riscv/andes.md (branch-on-bit pattern): Reference the forward label correctly in the long branch sequence. * config/riscv/peephole.md: Require operands to be a REG before asking for the REGNO. Diff: --- gcc/config/riscv/andes.md | 2 +- gcc/config/riscv/peephole.md | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/andes.md b/gcc/config/riscv/andes.md index 82563176b407..4b19fba5aa2f 100644 --- a/gcc/config/riscv/andes.md +++ b/gcc/config/riscv/andes.md @@ -61,7 +61,7 @@ "TARGET_XANDESPERF" { if (get_attr_length (insn) == 12) - return "nds.bb<any_eq:cs>\t%1,%2,%1f; jump\t%l0,ra; 1:"; + return "nds.bb<any_eq:cs>\t%1,%2,1f; jump\t%l0,ra; 1:"; return "nds.bb<any_eq:cs>\t%1,%2,%l0"; } diff --git a/gcc/config/riscv/peephole.md b/gcc/config/riscv/peephole.md index e49bc0426653..9191064c012c 100644 --- a/gcc/config/riscv/peephole.md +++ b/gcc/config/riscv/peephole.md @@ -29,6 +29,7 @@ (ashift:DI (match_dup 3) (match_operand 5 "const_int_operand")))] "TARGET_64BIT && INTVAL (operands[5]) < INTVAL (operands[2]) + && REG_P (operands[3]) && REG_P (operands[4]) && (REGNO (operands[3]) == REGNO (operands[4]) || peep2_reg_dead_p (3, operands[3]))" [(set (match_dup 0)
