https://gcc.gnu.org/g:7df74ad63dc03768c6339911ac1ed93c5c09158e

commit r17-5587-g7df74ad63dc03768c6339911ac1ed93c5c09158e
Author: Jeff Law <[email protected]>
Date:   Mon Oct 26 11:03:11 2026 -0600

    [RISC-V] Fix/simplify patterns for masked comparisons against zero
    
    Still digging through the various LLM spotted bugs.
    
    In this episode we have 3 patterns which can simplify equality comparisons 
of a
    masked register.  The precise form changes a bit, but the basic idea is to
    right shift out as many bit positions as possible with the mask simplifying
    down to a simm12 operand if at all possible. LLM review pointed out that the
    split RTL in the second pattern would not generate valid RTL for any mode 
other
    than word_mode.
    
    The patterns were using ANYI iterators for the masking operation and its
    operands, which in turn implies we're either doing a subreg or some kind of
    extension in the split RTL.  While we can technically support ANYI here it 
adds
    complexity for what appears to be no gain as I tried for a while (guiding 
the
    LLM) to construct a suitable testcase.
    
    Given the masking actually happens in word_mode, we might as well use X 
instead
    of ANYI.  That also drops the subreg from the split-rtl.  If we do find a
    testcase where matching ANYI would be helpful, we can always add it back and
    we'll have a viable testcase.
    
    Assisted-By: Claude for bug discovery and attempts to produce test
    
    Tested on riscv32-elf and riscv64-elf.  Pushing to the trunk.
    
    gcc/
            * config/riscv/riscv.md 
(branch<ANYI:mode>_shiftedarith_equals_zero):
            Use X rather than ANYI.  Drop subreg to X in split RTL.  Simplify
            pattern name accordingly.
            (branch<ANYI:mode>_shiftedmask_equals_zero): Similarly.
            (branch<ANYI:mode>_shiftedarith_<optab>_shifted): Similalry, but no
            change in split RTL.

Diff:
---
 gcc/config/riscv/riscv.md | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 0284512d72c2..898fa85ea626 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -3377,10 +3377,10 @@
 
 ;; Conditional branches
 
-(define_insn_and_split "*branch<ANYI:mode>_shiftedarith_equals_zero"
+(define_insn_and_split "*branch<mode>_shiftedarith_equals_zero"
   [(set (pc)
        (if_then_else (match_operator 1 "equality_operator"
-                      [(and:ANYI (match_operand:ANYI 2 "register_operand" "r")
+                      [(and:X (match_operand:X 2 "register_operand" "r")
                                  (match_operand 3 
"shifted_const_arith_operand" "i"))
                        (const_int 0)])
         (label_ref (match_operand 0 "" ""))
@@ -3389,7 +3389,7 @@
   "!SMALL_OPERAND (INTVAL (operands[3]))"
   "#"
   "&& reload_completed"
-  [(set (match_dup 4) (lshiftrt:X (subreg:X (match_dup 2) 0) (match_dup 6)))
+  [(set (match_dup 4) (lshiftrt:X (match_dup 2) (match_dup 6)))
    (set (match_dup 4) (match_dup 8))
    (set (pc) (if_then_else (match_op_dup 1 [(match_dup 4) (const_int 0)])
                           (label_ref (match_dup 0)) (pc)))]
@@ -3412,10 +3412,10 @@
 }
 [(set_attr "type" "branch")])
 
-(define_insn_and_split "*branch<ANYI:mode>_shiftedarith_<optab>_shifted"
+(define_insn_and_split "*branch<mode>_shiftedarith_<optab>_shifted"
   [(set (pc)
        (if_then_else (any_eq
-                   (and:ANYI (match_operand:ANYI 1 "register_operand" "r")
+                   (and:X (match_operand:X 1 "register_operand" "r")
                          (match_operand 2 "shifted_const_arith_operand" "i"))
                    (match_operand 3 "shifted_const_arith_operand" "i"))
         (label_ref (match_operand 0 "" ""))
@@ -3454,11 +3454,11 @@
 }
 [(set_attr "type" "branch")])
 
-(define_insn_and_split "*branch<ANYI:mode>_shiftedmask_equals_zero"
+(define_insn_and_split "*branch<mode>_shiftedmask_equals_zero"
   [(set (pc)
        (if_then_else (match_operator 1 "equality_operator"
-                      [(and:ANYI (match_operand:ANYI 2 "register_operand" "r")
-                                 (match_operand 3 "consecutive_bits_operand" 
"i"))
+                      [(and:X (match_operand:X 2 "register_operand" "r")
+                              (match_operand 3 "consecutive_bits_operand" "i"))
                        (const_int 0)])
         (label_ref (match_operand 0 "" ""))
         (pc)))
@@ -3468,7 +3468,7 @@
     && !SMALL_OPERAND (INTVAL (operands[3]))"
   "#"
   "&& reload_completed"
-  [(set (match_dup 4) (ashift:X (subreg:X (match_dup 2) 0) (match_dup 6)))
+  [(set (match_dup 4) (ashift:X (match_dup 2) (match_dup 6)))
    (set (match_dup 4) (lshiftrt:X (match_dup 4) (match_dup 7)))
    (set (pc) (if_then_else (match_op_dup 1 [(match_dup 4) (const_int 0)])
                           (label_ref (match_dup 0)) (pc)))]

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