https://gcc.gnu.org/g:cca520329eb7403bfcf9cb6fc4779bd380a5d0a7
commit cca520329eb7403bfcf9cb6fc4779bd380a5d0a7 Author: Michael Meissner <[email protected]> Date: Mon Oct 26 21:20:33 2026 -0400 Change how -mfloat16 is enabled by default. 2026-10-26 Michael Meissner <[email protected]> * config/rs6000/rs6000-cpus.def (TARGET_16BIT_FLOATING_POINT): Delete. (ISA_2_7_MASKS_SERVER): Don't set -mfloat16 here. * config/rs6000/rs6000.cc (rs6000_option_override_internal): Change how -mfloat16 is enabled by default. * config/rs6000/rs6000.h (TARGET_FLOAT16_MIN_HARDWARE): New macro. Diff: --- gcc/config/rs6000/rs6000-cpus.def | 12 +----------- gcc/config/rs6000/rs6000.cc | 15 ++++++++++++++- gcc/config/rs6000/rs6000.h | 8 ++++++++ 3 files changed, 23 insertions(+), 12 deletions(-) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index f06019c2d499..cac42403fd94 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -43,15 +43,6 @@ | OPTION_MASK_ALTIVEC \ | OPTION_MASK_VSX) -/* Determine whether to enable 16-bit floating point types on power8 systems - and above. */ -#if POWERPC_FLOAT16_DEFAULT -#define TARGET_16BIT_FLOATING_POINT OPTION_MASK_FLOAT16 - -#else -#define TARGET_16BIT_FLOATING_POINT 0 -#endif - /* For now, don't provide an embedded version of ISA 2.07. Do not set power8 fusion here, instead set it in rs6000.cc if we are tuning for a power8 system. */ @@ -61,8 +52,7 @@ | OPTION_MASK_CRYPTO \ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ | OPTION_MASK_QUAD_MEMORY \ - | OPTION_MASK_QUAD_MEMORY_ATOMIC \ - | TARGET_16BIT_FLOATING_POINT) + | OPTION_MASK_QUAD_MEMORY_ATOMIC) /* ISA masks setting fusion options. */ #define OTHER_FUSION_MASKS (OPTION_MASK_P8_FUSION \ diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 8107cd14a9a3..52598da86a53 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -4021,11 +4021,24 @@ rs6000_option_override_internal (bool global_init_p) } } + /* Enable -mfloat16 if it was configured, the user did not specify -mfloat16 + or -mno-float16, and we have the minimum hardware requirements to handle + 16-bit floating point. */ + if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT16) == 0) + { +#if POWERPC_FLOAT16_DEFAULT + if (TARGET_FLOAT16_MIN_HARDWARE) + rs6000_isa_flags |= OPTION_MASK_FLOAT16; + else +#endif + rs6000_isa_flags &= ~OPTION_MASK_FLOAT16; + } + /* 16-bit floating point needs 64-bit power8 at a minimum in order to load up 16-bit values into vector registers via loads/stores from GPRs and then using direct moves. Don't allow 16-bit float on big endian systems at the current time. */ - if (TARGET_FLOAT16 && (!TARGET_DIRECT_MOVE_64BIT || BYTES_BIG_ENDIAN)) + if (TARGET_FLOAT16 && !TARGET_FLOAT16_MIN_HARDWARE) { rs6000_isa_flags &= ~OPTION_MASK_FLOAT16; if (rs6000_isa_flags_explicit & OPTION_MASK_FLOAT16) diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index cfa365825aa4..d88c96292309 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -595,6 +595,14 @@ extern int rs6000_vector_align[]; #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \ && TARGET_POWERPC64) +/* Macro to say that we have the minimum hardware to enable 16-bit floating + point. We require a little endian 64-bit machine that supports at least + power8 with VSX support. */ +#define TARGET_FLOAT16_MIN_HARDWARE (TARGET_P8_VECTOR \ + && TARGET_POWERPC64 \ + && !BYTES_BIG_ENDIAN) + + /* Inlining allows targets to define the meanings of bits in target_info field of ipa_fn_summary by itself, the used bits for rs6000 are listed below. */
