https://gcc.gnu.org/g:4c8452662e95e3fa68543fb00ec6d6905bbd19c8
commit r17-5606-g4c8452662e95e3fa68543fb00ec6d6905bbd19c8 Author: Pan Li <[email protected]> Date: Sun Oct 25 21:06:05 2026 +0800 RISC-V: Add test cases for vfwmsac.vv reg overlap Add test cases for register group overlap, please note it is not overlap as much as possible. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-mf4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-mf2.c: New test. Signed-off-by: Pan Li <[email protected]> Diff: --- .../rvv/autovec/group_overlap/vfwmsac_vv-f16-m1.c | 64 ++++++++++++++++++++++ .../rvv/autovec/group_overlap/vfwmsac_vv-f16-m2.c | 56 +++++++++++++++++++ .../rvv/autovec/group_overlap/vfwmsac_vv-f16-m4.c | 52 ++++++++++++++++++ .../rvv/autovec/group_overlap/vfwmsac_vv-f16-mf2.c | 21 +++++++ .../rvv/autovec/group_overlap/vfwmsac_vv-f16-mf4.c | 21 +++++++ .../rvv/autovec/group_overlap/vfwmsac_vv-f32-m1.c | 64 ++++++++++++++++++++++ .../rvv/autovec/group_overlap/vfwmsac_vv-f32-m2.c | 56 +++++++++++++++++++ .../rvv/autovec/group_overlap/vfwmsac_vv-f32-m4.c | 52 ++++++++++++++++++ .../rvv/autovec/group_overlap/vfwmsac_vv-f32-mf2.c | 21 +++++++ 9 files changed, 407 insertions(+) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m1.c new file mode 100644 index 000000000000..dff01bb129a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m1.c @@ -0,0 +1,64 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +static inline vfloat16m2_t +reinterpret_f32m2_f16m2 (vfloat32m2_t v) +{ + return __riscv_vreinterpret_v_i16m2_f16m2 ( + __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vreinterpret_v_f32m2_i32m2 (v))); +} + +DEF_GROUP_OVERLAP_TERNARY_0( + __riscv_vsetvlmax_e16m1, + vfloat16m1_t, + vfloat32m2_t, + __riscv_vle16_v_f16m1, + __riscv_vle32_v_f32m2, + __riscv_vfwmsac_vv_f32m2, + __riscv_vse32_v_f32m2, + vfwmsac_vv, + LOOP_DUAL_WIDEN_TERNARY_BODY_X16) + +DEF_GROUP_OVERLAP_TERNARY_1( + __riscv_vsetvlmax_e16m1, + vfloat16m1_t, + vfloat32m2_t, + vfloat16m2_t, + __riscv_vle16_v_f16m1, + __riscv_vle32_v_f32m2, + reinterpret_f32m2_f16m2, + __riscv_vget_v_f16m2_f16m1, + __riscv_vfwmsac_vv_f32m2, + __riscv_vse32_v_f32m2, + vfwmsac_vv, + LOOP_DUAL_WIDEN_TERNARY_BODY_OVERLAP_X2) + +/* ternary_0: the accumulator occupies the whole destination register group and + is live when the narrowed sources are read, so no source can be allocated + inside the destination register group. */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v12,v30,v29([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v4,v16,v15([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v2,v0,v31([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v8,v14,v1([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v30,v28,v27([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v28,v26,v25([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v6,v20,v19([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v26,v24,v23([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v2,v18,v17([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v10,v1,v15([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v24,v22,v21([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v14,v19,v17([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v16,v21,v23([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v18,v20,v22([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v20,v0,v1([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v22,v0,v1([^0-9]|$)} 1 } } */ + +/* ternary_1: each narrowed source is the highest-numbered half of its own + accumulator, thus it overlaps the highest-numbered part of the destination + register group. Without the group overlap the sources would have to be + copied out to a disjoint register group first. */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v4,v5,v8([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v2,v3,v1([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m2.c new file mode 100644 index 000000000000..dc74fd44a6e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m2.c @@ -0,0 +1,56 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +static inline vfloat16m4_t +reinterpret_f32m4_f16m4 (vfloat32m4_t v) +{ + return __riscv_vreinterpret_v_i16m4_f16m4 ( + __riscv_vreinterpret_v_i32m4_i16m4 (__riscv_vreinterpret_v_f32m4_i32m4 (v))); +} + +DEF_GROUP_OVERLAP_TERNARY_0( + __riscv_vsetvlmax_e16m2, + vfloat16m2_t, + vfloat32m4_t, + __riscv_vle16_v_f16m2, + __riscv_vle32_v_f32m4, + __riscv_vfwmsac_vv_f32m4, + __riscv_vse32_v_f32m4, + vfwmsac_vv, + LOOP_DUAL_WIDEN_TERNARY_BODY_X8) + +DEF_GROUP_OVERLAP_TERNARY_1( + __riscv_vsetvlmax_e16m2, + vfloat16m2_t, + vfloat32m4_t, + vfloat16m4_t, + __riscv_vle16_v_f16m2, + __riscv_vle32_v_f32m4, + reinterpret_f32m4_f16m4, + __riscv_vget_v_f16m4_f16m2, + __riscv_vfwmsac_vv_f32m4, + __riscv_vse32_v_f32m4, + vfwmsac_vv, + LOOP_DUAL_WIDEN_TERNARY_BODY_OVERLAP_X2) + +/* ternary_0: the accumulator occupies the whole destination register group and + is live when the narrowed sources are read, so no source can be allocated + inside the destination register group. */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v8,v0,v30([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v0,v28,v26([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v28,v24,v22([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v24,v20,v18([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v20,v16,v14([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v16,v12,v10([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v12,v8,v6([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v8,v4,v2([^0-9]|$)} 1 } } */ + +/* ternary_1: each narrowed source is the highest-numbered half of its own + accumulator, thus it overlaps the highest-numbered part of the destination + register group. Without the group overlap the sources would have to be + copied out to a disjoint register group first. */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v8,v10,v16([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v4,v6,v2([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m4.c new file mode 100644 index 000000000000..b27941106cd9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m4.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +static inline vfloat16m8_t +reinterpret_f32m8_f16m8 (vfloat32m8_t v) +{ + return __riscv_vreinterpret_v_i16m8_f16m8 ( + __riscv_vreinterpret_v_i32m8_i16m8 (__riscv_vreinterpret_v_f32m8_i32m8 (v))); +} + +DEF_GROUP_OVERLAP_TERNARY_0( + __riscv_vsetvlmax_e16m4, + vfloat16m4_t, + vfloat32m8_t, + __riscv_vle16_v_f16m4, + __riscv_vle32_v_f32m8, + __riscv_vfwmsac_vv_f32m8, + __riscv_vse32_v_f32m8, + vfwmsac_vv, + LOOP_DUAL_WIDEN_TERNARY_BODY_X4) + +DEF_GROUP_OVERLAP_TERNARY_1( + __riscv_vsetvlmax_e16m4, + vfloat16m4_t, + vfloat32m8_t, + vfloat16m8_t, + __riscv_vle16_v_f16m4, + __riscv_vle32_v_f32m8, + reinterpret_f32m8_f16m8, + __riscv_vget_v_f16m8_f16m4, + __riscv_vfwmsac_vv_f32m8, + __riscv_vse32_v_f32m8, + vfwmsac_vv, + LOOP_DUAL_WIDEN_TERNARY_BODY_OVERLAP_X2) + +/* ternary_0: the accumulator occupies the whole destination register group and + is live when the narrowed sources are read, so no source can be allocated + inside the destination register group. */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v16,v0,v4([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v0,v28,v20([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v24,v16,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v16,v8,v12([^0-9]|$)} 1 } } */ + +/* ternary_1: each narrowed source is the highest-numbered half of its own + accumulator, thus it overlaps the highest-numbered part of the destination + register group. Without the group overlap the sources would have to be + copied out to a disjoint register group first. */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v16,v20,v0([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v8,v12,v4([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-mf2.c new file mode 100644 index 000000000000..0a32d56aed09 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-mf2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_TERNARY_0( + __riscv_vsetvlmax_e16m1, + vfloat16mf2_t, + vfloat32m1_t, + __riscv_vle16_v_f16mf2, + __riscv_vle32_v_f32m1, + __riscv_vfwmsac_vv_f32m1, + __riscv_vse32_v_f32m1, + vfwmsac_vv, + LOOP_DUAL_WIDEN_TERNARY_BODY_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap either source at all. */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv} 16 } } */ +/* { dg-final { scan-assembler-not {vfwmsac\.vv\s+(v[0-9]+),\1,} } } */ +/* { dg-final { scan-assembler-not {vfwmsac\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-mf4.c new file mode 100644 index 000000000000..741275928354 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-mf4.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_TERNARY_0( + __riscv_vsetvlmax_e16m1, + vfloat16mf4_t, + vfloat32mf2_t, + __riscv_vle16_v_f16mf4, + __riscv_vle32_v_f32mf2, + __riscv_vfwmsac_vv_f32mf2, + __riscv_vse32_v_f32mf2, + vfwmsac_vv, + LOOP_DUAL_WIDEN_TERNARY_BODY_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap either source at all. */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv} 16 } } */ +/* { dg-final { scan-assembler-not {vfwmsac\.vv\s+(v[0-9]+),\1,} } } */ +/* { dg-final { scan-assembler-not {vfwmsac\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m1.c new file mode 100644 index 000000000000..8c0c41ca6bba --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m1.c @@ -0,0 +1,64 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +static inline vfloat32m2_t +reinterpret_f64m2_f32m2 (vfloat64m2_t v) +{ + return __riscv_vreinterpret_v_i32m2_f32m2 ( + __riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (v))); +} + +DEF_GROUP_OVERLAP_TERNARY_0( + __riscv_vsetvlmax_e32m1, + vfloat32m1_t, + vfloat64m2_t, + __riscv_vle32_v_f32m1, + __riscv_vle64_v_f64m2, + __riscv_vfwmsac_vv_f64m2, + __riscv_vse64_v_f64m2, + vfwmsac_vv, + LOOP_DUAL_WIDEN_TERNARY_BODY_X16) + +DEF_GROUP_OVERLAP_TERNARY_1( + __riscv_vsetvlmax_e32m1, + vfloat32m1_t, + vfloat64m2_t, + vfloat32m2_t, + __riscv_vle32_v_f32m1, + __riscv_vle64_v_f64m2, + reinterpret_f64m2_f32m2, + __riscv_vget_v_f32m2_f32m1, + __riscv_vfwmsac_vv_f64m2, + __riscv_vse64_v_f64m2, + vfwmsac_vv, + LOOP_DUAL_WIDEN_TERNARY_BODY_OVERLAP_X2) + +/* ternary_0: the accumulator occupies the whole destination register group and + is live when the narrowed sources are read, so no source can be allocated + inside the destination register group. */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v12,v30,v29([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v4,v16,v15([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v2,v0,v31([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v8,v14,v1([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v30,v28,v27([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v28,v26,v25([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v6,v20,v19([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v26,v24,v23([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v2,v18,v17([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v10,v1,v15([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v24,v22,v21([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v14,v19,v17([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v16,v21,v23([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v18,v20,v22([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v20,v0,v1([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v22,v0,v1([^0-9]|$)} 1 } } */ + +/* ternary_1: each narrowed source is the highest-numbered half of its own + accumulator, thus it overlaps the highest-numbered part of the destination + register group. Without the group overlap the sources would have to be + copied out to a disjoint register group first. */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v4,v5,v8([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v2,v3,v1([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m2.c new file mode 100644 index 000000000000..3156cc21fd79 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m2.c @@ -0,0 +1,56 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +static inline vfloat32m4_t +reinterpret_f64m4_f32m4 (vfloat64m4_t v) +{ + return __riscv_vreinterpret_v_i32m4_f32m4 ( + __riscv_vreinterpret_v_i64m4_i32m4 (__riscv_vreinterpret_v_f64m4_i64m4 (v))); +} + +DEF_GROUP_OVERLAP_TERNARY_0( + __riscv_vsetvlmax_e32m2, + vfloat32m2_t, + vfloat64m4_t, + __riscv_vle32_v_f32m2, + __riscv_vle64_v_f64m4, + __riscv_vfwmsac_vv_f64m4, + __riscv_vse64_v_f64m4, + vfwmsac_vv, + LOOP_DUAL_WIDEN_TERNARY_BODY_X8) + +DEF_GROUP_OVERLAP_TERNARY_1( + __riscv_vsetvlmax_e32m2, + vfloat32m2_t, + vfloat64m4_t, + vfloat32m4_t, + __riscv_vle32_v_f32m2, + __riscv_vle64_v_f64m4, + reinterpret_f64m4_f32m4, + __riscv_vget_v_f32m4_f32m2, + __riscv_vfwmsac_vv_f64m4, + __riscv_vse64_v_f64m4, + vfwmsac_vv, + LOOP_DUAL_WIDEN_TERNARY_BODY_OVERLAP_X2) + +/* ternary_0: the accumulator occupies the whole destination register group and + is live when the narrowed sources are read, so no source can be allocated + inside the destination register group. */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v8,v0,v30([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v0,v28,v26([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v28,v24,v22([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v24,v20,v18([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v20,v16,v14([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v16,v12,v10([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v12,v8,v6([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v8,v4,v2([^0-9]|$)} 1 } } */ + +/* ternary_1: each narrowed source is the highest-numbered half of its own + accumulator, thus it overlaps the highest-numbered part of the destination + register group. Without the group overlap the sources would have to be + copied out to a disjoint register group first. */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v8,v10,v16([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v4,v6,v2([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m4.c new file mode 100644 index 000000000000..3c62fda04fd3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m4.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +static inline vfloat32m8_t +reinterpret_f64m8_f32m8 (vfloat64m8_t v) +{ + return __riscv_vreinterpret_v_i32m8_f32m8 ( + __riscv_vreinterpret_v_i64m8_i32m8 (__riscv_vreinterpret_v_f64m8_i64m8 (v))); +} + +DEF_GROUP_OVERLAP_TERNARY_0( + __riscv_vsetvlmax_e32m4, + vfloat32m4_t, + vfloat64m8_t, + __riscv_vle32_v_f32m4, + __riscv_vle64_v_f64m8, + __riscv_vfwmsac_vv_f64m8, + __riscv_vse64_v_f64m8, + vfwmsac_vv, + LOOP_DUAL_WIDEN_TERNARY_BODY_X4) + +DEF_GROUP_OVERLAP_TERNARY_1( + __riscv_vsetvlmax_e32m4, + vfloat32m4_t, + vfloat64m8_t, + vfloat32m8_t, + __riscv_vle32_v_f32m4, + __riscv_vle64_v_f64m8, + reinterpret_f64m8_f32m8, + __riscv_vget_v_f32m8_f32m4, + __riscv_vfwmsac_vv_f64m8, + __riscv_vse64_v_f64m8, + vfwmsac_vv, + LOOP_DUAL_WIDEN_TERNARY_BODY_OVERLAP_X2) + +/* ternary_0: the accumulator occupies the whole destination register group and + is live when the narrowed sources are read, so no source can be allocated + inside the destination register group. */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v16,v0,v4([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v0,v28,v20([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v24,v16,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v16,v8,v12([^0-9]|$)} 1 } } */ + +/* ternary_1: each narrowed source is the highest-numbered half of its own + accumulator, thus it overlaps the highest-numbered part of the destination + register group. Without the group overlap the sources would have to be + copied out to a disjoint register group first. */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v16,v20,v0([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v8,v12,v4([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-mf2.c new file mode 100644 index 000000000000..c25f2af6eef0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-mf2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_TERNARY_0( + __riscv_vsetvlmax_e32m1, + vfloat32mf2_t, + vfloat64m1_t, + __riscv_vle32_v_f32mf2, + __riscv_vle64_v_f64m1, + __riscv_vfwmsac_vv_f64m1, + __riscv_vse64_v_f64m1, + vfwmsac_vv, + LOOP_DUAL_WIDEN_TERNARY_BODY_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap either source at all. */ +/* { dg-final { scan-assembler-times {vfwmsac\.vv} 16 } } */ +/* { dg-final { scan-assembler-not {vfwmsac\.vv\s+(v[0-9]+),\1,} } } */ +/* { dg-final { scan-assembler-not {vfwmsac\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */
