https://gcc.gnu.org/g:62e0fe6ce26047129244e7a1c5f0fb829f67a309
commit r17-5716-g62e0fe6ce26047129244e7a1c5f0fb829f67a309 Author: Pan Li <[email protected]> Date: Wed Oct 28 10:36:35 2026 +0800 RISC-V: Disable RVV register overlap for vfw{macc,msac}.vv [PR target/128162] Revert the register overlap of the widening multiply-add insn vfw{macc,msac}.vv and the related test cases. The insn reads the vd as the accumulator with EEW = 2 * SEW, while the vs1 and vs2 are read with EEW = SEW. The section 5.2 of the vector spec reserves any encoding in which one vector register supplies source operands with two or more different EEWs. Thus, the vs1 and vs2 must not overlap the vd register group, even in the highest-numbered part. For example, below asm dump is reserved as the v3 is read with both the EEW = 32 and the EEW = 16. vfwmacc.vv v2,v3,v4 # LMUL = 1, SEW = 16 This reverts commit(s): dafa6930eb5 RISC-V: Allow RVV register overlap for vfw{macc,msac}.vv cfb973b3441 RISC-V: Add test cases for vfwmacc.vv reg overlap 4c8452662e9 RISC-V: Add test cases for vfwmsac.vv reg overlap 9c73440b6f8 RISC-V: Add more test cases for vfw{macc,msac}.vv PR target/128162 gcc/ChangeLog: * config/riscv/vector.md: Revert Wvr constraint to the early clobber vr. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-m1.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-m2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-m4.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-mf2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-mf4.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f32-m1.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f32-m2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f32-m4.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f32-mf2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m1.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m4.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-mf2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-mf4.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m1.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m4.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-mf2.c: Removed. * gcc.target/riscv/rvv/base/pr112431-61.c: Removed. * gcc.target/riscv/rvv/base/pr112431-62.c: Removed. Signed-off-by: Pan Li <[email protected]> Diff: --- gcc/config/riscv/vector.md | 20 +++---- .../rvv/autovec/group_overlap/vfwmacc_vv-f16-m1.c | 64 ---------------------- .../rvv/autovec/group_overlap/vfwmacc_vv-f16-m2.c | 56 ------------------- .../rvv/autovec/group_overlap/vfwmacc_vv-f16-m4.c | 52 ------------------ .../rvv/autovec/group_overlap/vfwmacc_vv-f16-mf2.c | 21 ------- .../rvv/autovec/group_overlap/vfwmacc_vv-f16-mf4.c | 21 ------- .../rvv/autovec/group_overlap/vfwmacc_vv-f32-m1.c | 64 ---------------------- .../rvv/autovec/group_overlap/vfwmacc_vv-f32-m2.c | 56 ------------------- .../rvv/autovec/group_overlap/vfwmacc_vv-f32-m4.c | 52 ------------------ .../rvv/autovec/group_overlap/vfwmacc_vv-f32-mf2.c | 21 ------- .../rvv/autovec/group_overlap/vfwmsac_vv-f16-m1.c | 64 ---------------------- .../rvv/autovec/group_overlap/vfwmsac_vv-f16-m2.c | 56 ------------------- .../rvv/autovec/group_overlap/vfwmsac_vv-f16-m4.c | 52 ------------------ .../rvv/autovec/group_overlap/vfwmsac_vv-f16-mf2.c | 21 ------- .../rvv/autovec/group_overlap/vfwmsac_vv-f16-mf4.c | 21 ------- .../rvv/autovec/group_overlap/vfwmsac_vv-f32-m1.c | 64 ---------------------- .../rvv/autovec/group_overlap/vfwmsac_vv-f32-m2.c | 56 ------------------- .../rvv/autovec/group_overlap/vfwmsac_vv-f32-m4.c | 52 ------------------ .../rvv/autovec/group_overlap/vfwmsac_vv-f32-mf2.c | 21 ------- .../gcc.target/riscv/rvv/base/pr112431-61.c | 59 -------------------- .../gcc.target/riscv/rvv/base/pr112431-62.c | 59 -------------------- 21 files changed, 10 insertions(+), 942 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 8f7db534e321..e0b08bd5a88e 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7436,25 +7436,25 @@ ;; ------------------------------------------------------------------------------- (define_insn "@pred_widen_mul_<optab><mode>" - [(set (match_operand:VWEXTF 0 "register_operand" "=vr, vd") + [(set (match_operand:VWEXTF 0 "register_operand" "=&vr") (if_then_else:VWEXTF (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" "Wc1, vm") - (match_operand 5 "vector_length_operand" "rvl,rvl") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (match_operand 9 "const_int_operand" " i, i") + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1") + (match_operand 5 "vector_length_operand" " rvl") + (match_operand 6 "const_int_operand" " i") + (match_operand 7 "const_int_operand" " i") + (match_operand 8 "const_int_operand" " i") + (match_operand 9 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM) (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VWEXTF (mult:VWEXTF (float_extend:VWEXTF - (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "Wvr,Wvr")) + (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr")) (float_extend:VWEXTF - (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "Wvr,Wvr"))) - (match_operand:VWEXTF 2 "register_operand" " 0, 0")) + (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))) + (match_operand:VWEXTF 2 "register_operand" " 0")) (match_dup 2)))] "TARGET_VECTOR" "vfw<macc_msac>.vv\t%0,%3,%4%p1" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-m1.c deleted file mode 100644 index d8c1966adb9d..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-m1.c +++ /dev/null @@ -1,64 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ - -#include "group_overlap.h" - -static inline vfloat16m2_t -reinterpret_f32m2_f16m2 (vfloat32m2_t v) -{ - return __riscv_vreinterpret_v_i16m2_f16m2 ( - __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vreinterpret_v_f32m2_i32m2 (v))); -} - -DEF_GROUP_OVERLAP_TERNARY_0( - __riscv_vsetvlmax_e16m1, - vfloat16m1_t, - vfloat32m2_t, - __riscv_vle16_v_f16m1, - __riscv_vle32_v_f32m2, - __riscv_vfwmacc_vv_f32m2, - __riscv_vse32_v_f32m2, - vfwmacc_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_X16) - -DEF_GROUP_OVERLAP_TERNARY_1( - __riscv_vsetvlmax_e16m1, - vfloat16m1_t, - vfloat32m2_t, - vfloat16m2_t, - __riscv_vle16_v_f16m1, - __riscv_vle32_v_f32m2, - reinterpret_f32m2_f16m2, - __riscv_vget_v_f16m2_f16m1, - __riscv_vfwmacc_vv_f32m2, - __riscv_vse32_v_f32m2, - vfwmacc_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_OVERLAP_X2) - -/* ternary_0: the accumulator occupies the whole destination register group and - is live when the narrowed sources are read, so no source can be allocated - inside the destination register group. */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v12,v30,v29([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v4,v16,v15([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v2,v0,v31([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v8,v14,v1([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v30,v28,v27([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v28,v26,v25([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v6,v20,v19([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v26,v24,v23([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v2,v18,v17([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v10,v1,v15([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v24,v22,v21([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v14,v19,v17([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v16,v21,v23([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v18,v20,v22([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v20,v0,v1([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v22,v0,v1([^0-9]|$)} 1 } } */ - -/* ternary_1: each narrowed source is the highest-numbered half of its own - accumulator, thus it overlaps the highest-numbered part of the destination - register group. Without the group overlap the sources would have to be - copied out to a disjoint register group first. */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v4,v5,v8([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v2,v3,v1([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-m2.c deleted file mode 100644 index 77af7cac858b..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-m2.c +++ /dev/null @@ -1,56 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ - -#include "group_overlap.h" - -static inline vfloat16m4_t -reinterpret_f32m4_f16m4 (vfloat32m4_t v) -{ - return __riscv_vreinterpret_v_i16m4_f16m4 ( - __riscv_vreinterpret_v_i32m4_i16m4 (__riscv_vreinterpret_v_f32m4_i32m4 (v))); -} - -DEF_GROUP_OVERLAP_TERNARY_0( - __riscv_vsetvlmax_e16m2, - vfloat16m2_t, - vfloat32m4_t, - __riscv_vle16_v_f16m2, - __riscv_vle32_v_f32m4, - __riscv_vfwmacc_vv_f32m4, - __riscv_vse32_v_f32m4, - vfwmacc_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_X8) - -DEF_GROUP_OVERLAP_TERNARY_1( - __riscv_vsetvlmax_e16m2, - vfloat16m2_t, - vfloat32m4_t, - vfloat16m4_t, - __riscv_vle16_v_f16m2, - __riscv_vle32_v_f32m4, - reinterpret_f32m4_f16m4, - __riscv_vget_v_f16m4_f16m2, - __riscv_vfwmacc_vv_f32m4, - __riscv_vse32_v_f32m4, - vfwmacc_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_OVERLAP_X2) - -/* ternary_0: the accumulator occupies the whole destination register group and - is live when the narrowed sources are read, so no source can be allocated - inside the destination register group. */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v8,v0,v30([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v0,v28,v26([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v28,v24,v22([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v24,v20,v18([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v20,v16,v14([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v16,v12,v10([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v12,v8,v6([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v8,v4,v2([^0-9]|$)} 1 } } */ - -/* ternary_1: each narrowed source is the highest-numbered half of its own - accumulator, thus it overlaps the highest-numbered part of the destination - register group. Without the group overlap the sources would have to be - copied out to a disjoint register group first. */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v8,v10,v16([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v4,v6,v2([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-m4.c deleted file mode 100644 index 919706343a41..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-m4.c +++ /dev/null @@ -1,52 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ - -#include "group_overlap.h" - -static inline vfloat16m8_t -reinterpret_f32m8_f16m8 (vfloat32m8_t v) -{ - return __riscv_vreinterpret_v_i16m8_f16m8 ( - __riscv_vreinterpret_v_i32m8_i16m8 (__riscv_vreinterpret_v_f32m8_i32m8 (v))); -} - -DEF_GROUP_OVERLAP_TERNARY_0( - __riscv_vsetvlmax_e16m4, - vfloat16m4_t, - vfloat32m8_t, - __riscv_vle16_v_f16m4, - __riscv_vle32_v_f32m8, - __riscv_vfwmacc_vv_f32m8, - __riscv_vse32_v_f32m8, - vfwmacc_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_X4) - -DEF_GROUP_OVERLAP_TERNARY_1( - __riscv_vsetvlmax_e16m4, - vfloat16m4_t, - vfloat32m8_t, - vfloat16m8_t, - __riscv_vle16_v_f16m4, - __riscv_vle32_v_f32m8, - reinterpret_f32m8_f16m8, - __riscv_vget_v_f16m8_f16m4, - __riscv_vfwmacc_vv_f32m8, - __riscv_vse32_v_f32m8, - vfwmacc_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_OVERLAP_X2) - -/* ternary_0: the accumulator occupies the whole destination register group and - is live when the narrowed sources are read, so no source can be allocated - inside the destination register group. */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v16,v0,v4([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v0,v28,v20([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v24,v16,v12([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v16,v8,v12([^0-9]|$)} 1 } } */ - -/* ternary_1: each narrowed source is the highest-numbered half of its own - accumulator, thus it overlaps the highest-numbered part of the destination - register group. Without the group overlap the sources would have to be - copied out to a disjoint register group first. */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v16,v20,v0([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v8,v12,v4([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-mf2.c deleted file mode 100644 index cd31b9ef2ee6..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-mf2.c +++ /dev/null @@ -1,21 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ - -#include "group_overlap.h" - -DEF_GROUP_OVERLAP_TERNARY_0( - __riscv_vsetvlmax_e16m1, - vfloat16mf2_t, - vfloat32m1_t, - __riscv_vle16_v_f16mf2, - __riscv_vle32_v_f32m1, - __riscv_vfwmacc_vv_f32m1, - __riscv_vse32_v_f32m1, - vfwmacc_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_X16) - -/* The fractional LMUL source has EMUL < 1, thus the widened destination - register group must not overlap either source at all. */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv} 16 } } */ -/* { dg-final { scan-assembler-not {vfwmacc\.vv\s+(v[0-9]+),\1,} } } */ -/* { dg-final { scan-assembler-not {vfwmacc\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-mf4.c deleted file mode 100644 index ac8a8d519c7b..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f16-mf4.c +++ /dev/null @@ -1,21 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ - -#include "group_overlap.h" - -DEF_GROUP_OVERLAP_TERNARY_0( - __riscv_vsetvlmax_e16m1, - vfloat16mf4_t, - vfloat32mf2_t, - __riscv_vle16_v_f16mf4, - __riscv_vle32_v_f32mf2, - __riscv_vfwmacc_vv_f32mf2, - __riscv_vse32_v_f32mf2, - vfwmacc_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_X16) - -/* The fractional LMUL source has EMUL < 1, thus the widened destination - register group must not overlap either source at all. */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv} 16 } } */ -/* { dg-final { scan-assembler-not {vfwmacc\.vv\s+(v[0-9]+),\1,} } } */ -/* { dg-final { scan-assembler-not {vfwmacc\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f32-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f32-m1.c deleted file mode 100644 index 9bef07d47f98..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f32-m1.c +++ /dev/null @@ -1,64 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ - -#include "group_overlap.h" - -static inline vfloat32m2_t -reinterpret_f64m2_f32m2 (vfloat64m2_t v) -{ - return __riscv_vreinterpret_v_i32m2_f32m2 ( - __riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (v))); -} - -DEF_GROUP_OVERLAP_TERNARY_0( - __riscv_vsetvlmax_e32m1, - vfloat32m1_t, - vfloat64m2_t, - __riscv_vle32_v_f32m1, - __riscv_vle64_v_f64m2, - __riscv_vfwmacc_vv_f64m2, - __riscv_vse64_v_f64m2, - vfwmacc_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_X16) - -DEF_GROUP_OVERLAP_TERNARY_1( - __riscv_vsetvlmax_e32m1, - vfloat32m1_t, - vfloat64m2_t, - vfloat32m2_t, - __riscv_vle32_v_f32m1, - __riscv_vle64_v_f64m2, - reinterpret_f64m2_f32m2, - __riscv_vget_v_f32m2_f32m1, - __riscv_vfwmacc_vv_f64m2, - __riscv_vse64_v_f64m2, - vfwmacc_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_OVERLAP_X2) - -/* ternary_0: the accumulator occupies the whole destination register group and - is live when the narrowed sources are read, so no source can be allocated - inside the destination register group. */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v12,v30,v29([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v4,v16,v15([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v2,v0,v31([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v8,v14,v1([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v30,v28,v27([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v28,v26,v25([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v6,v20,v19([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v26,v24,v23([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v2,v18,v17([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v10,v1,v15([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v24,v22,v21([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v14,v19,v17([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v16,v21,v23([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v18,v20,v22([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v20,v0,v1([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v22,v0,v1([^0-9]|$)} 1 } } */ - -/* ternary_1: each narrowed source is the highest-numbered half of its own - accumulator, thus it overlaps the highest-numbered part of the destination - register group. Without the group overlap the sources would have to be - copied out to a disjoint register group first. */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v4,v5,v8([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v2,v3,v1([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f32-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f32-m2.c deleted file mode 100644 index 634acbaac9dd..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f32-m2.c +++ /dev/null @@ -1,56 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ - -#include "group_overlap.h" - -static inline vfloat32m4_t -reinterpret_f64m4_f32m4 (vfloat64m4_t v) -{ - return __riscv_vreinterpret_v_i32m4_f32m4 ( - __riscv_vreinterpret_v_i64m4_i32m4 (__riscv_vreinterpret_v_f64m4_i64m4 (v))); -} - -DEF_GROUP_OVERLAP_TERNARY_0( - __riscv_vsetvlmax_e32m2, - vfloat32m2_t, - vfloat64m4_t, - __riscv_vle32_v_f32m2, - __riscv_vle64_v_f64m4, - __riscv_vfwmacc_vv_f64m4, - __riscv_vse64_v_f64m4, - vfwmacc_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_X8) - -DEF_GROUP_OVERLAP_TERNARY_1( - __riscv_vsetvlmax_e32m2, - vfloat32m2_t, - vfloat64m4_t, - vfloat32m4_t, - __riscv_vle32_v_f32m2, - __riscv_vle64_v_f64m4, - reinterpret_f64m4_f32m4, - __riscv_vget_v_f32m4_f32m2, - __riscv_vfwmacc_vv_f64m4, - __riscv_vse64_v_f64m4, - vfwmacc_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_OVERLAP_X2) - -/* ternary_0: the accumulator occupies the whole destination register group and - is live when the narrowed sources are read, so no source can be allocated - inside the destination register group. */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v8,v0,v30([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v0,v28,v26([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v28,v24,v22([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v24,v20,v18([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v20,v16,v14([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v16,v12,v10([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v12,v8,v6([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v8,v4,v2([^0-9]|$)} 1 } } */ - -/* ternary_1: each narrowed source is the highest-numbered half of its own - accumulator, thus it overlaps the highest-numbered part of the destination - register group. Without the group overlap the sources would have to be - copied out to a disjoint register group first. */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v8,v10,v16([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v4,v6,v2([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f32-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f32-m4.c deleted file mode 100644 index 3909a632da79..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f32-m4.c +++ /dev/null @@ -1,52 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ - -#include "group_overlap.h" - -static inline vfloat32m8_t -reinterpret_f64m8_f32m8 (vfloat64m8_t v) -{ - return __riscv_vreinterpret_v_i32m8_f32m8 ( - __riscv_vreinterpret_v_i64m8_i32m8 (__riscv_vreinterpret_v_f64m8_i64m8 (v))); -} - -DEF_GROUP_OVERLAP_TERNARY_0( - __riscv_vsetvlmax_e32m4, - vfloat32m4_t, - vfloat64m8_t, - __riscv_vle32_v_f32m4, - __riscv_vle64_v_f64m8, - __riscv_vfwmacc_vv_f64m8, - __riscv_vse64_v_f64m8, - vfwmacc_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_X4) - -DEF_GROUP_OVERLAP_TERNARY_1( - __riscv_vsetvlmax_e32m4, - vfloat32m4_t, - vfloat64m8_t, - vfloat32m8_t, - __riscv_vle32_v_f32m4, - __riscv_vle64_v_f64m8, - reinterpret_f64m8_f32m8, - __riscv_vget_v_f32m8_f32m4, - __riscv_vfwmacc_vv_f64m8, - __riscv_vse64_v_f64m8, - vfwmacc_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_OVERLAP_X2) - -/* ternary_0: the accumulator occupies the whole destination register group and - is live when the narrowed sources are read, so no source can be allocated - inside the destination register group. */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v16,v0,v4([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v0,v28,v20([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v24,v16,v12([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v16,v8,v12([^0-9]|$)} 1 } } */ - -/* ternary_1: each narrowed source is the highest-numbered half of its own - accumulator, thus it overlaps the highest-numbered part of the destination - register group. Without the group overlap the sources would have to be - copied out to a disjoint register group first. */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v16,v20,v0([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv\s+v8,v12,v4([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f32-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f32-mf2.c deleted file mode 100644 index 495db5b5c748..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmacc_vv-f32-mf2.c +++ /dev/null @@ -1,21 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ - -#include "group_overlap.h" - -DEF_GROUP_OVERLAP_TERNARY_0( - __riscv_vsetvlmax_e32m1, - vfloat32mf2_t, - vfloat64m1_t, - __riscv_vle32_v_f32mf2, - __riscv_vle64_v_f64m1, - __riscv_vfwmacc_vv_f64m1, - __riscv_vse64_v_f64m1, - vfwmacc_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_X16) - -/* The fractional LMUL source has EMUL < 1, thus the widened destination - register group must not overlap either source at all. */ -/* { dg-final { scan-assembler-times {vfwmacc\.vv} 16 } } */ -/* { dg-final { scan-assembler-not {vfwmacc\.vv\s+(v[0-9]+),\1,} } } */ -/* { dg-final { scan-assembler-not {vfwmacc\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m1.c deleted file mode 100644 index dff01bb129a6..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m1.c +++ /dev/null @@ -1,64 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ - -#include "group_overlap.h" - -static inline vfloat16m2_t -reinterpret_f32m2_f16m2 (vfloat32m2_t v) -{ - return __riscv_vreinterpret_v_i16m2_f16m2 ( - __riscv_vreinterpret_v_i32m2_i16m2 (__riscv_vreinterpret_v_f32m2_i32m2 (v))); -} - -DEF_GROUP_OVERLAP_TERNARY_0( - __riscv_vsetvlmax_e16m1, - vfloat16m1_t, - vfloat32m2_t, - __riscv_vle16_v_f16m1, - __riscv_vle32_v_f32m2, - __riscv_vfwmsac_vv_f32m2, - __riscv_vse32_v_f32m2, - vfwmsac_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_X16) - -DEF_GROUP_OVERLAP_TERNARY_1( - __riscv_vsetvlmax_e16m1, - vfloat16m1_t, - vfloat32m2_t, - vfloat16m2_t, - __riscv_vle16_v_f16m1, - __riscv_vle32_v_f32m2, - reinterpret_f32m2_f16m2, - __riscv_vget_v_f16m2_f16m1, - __riscv_vfwmsac_vv_f32m2, - __riscv_vse32_v_f32m2, - vfwmsac_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_OVERLAP_X2) - -/* ternary_0: the accumulator occupies the whole destination register group and - is live when the narrowed sources are read, so no source can be allocated - inside the destination register group. */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v12,v30,v29([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v4,v16,v15([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v2,v0,v31([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v8,v14,v1([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v30,v28,v27([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v28,v26,v25([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v6,v20,v19([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v26,v24,v23([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v2,v18,v17([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v10,v1,v15([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v24,v22,v21([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v14,v19,v17([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v16,v21,v23([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v18,v20,v22([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v20,v0,v1([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v22,v0,v1([^0-9]|$)} 1 } } */ - -/* ternary_1: each narrowed source is the highest-numbered half of its own - accumulator, thus it overlaps the highest-numbered part of the destination - register group. Without the group overlap the sources would have to be - copied out to a disjoint register group first. */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v4,v5,v8([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v2,v3,v1([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m2.c deleted file mode 100644 index dc74fd44a6e3..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m2.c +++ /dev/null @@ -1,56 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ - -#include "group_overlap.h" - -static inline vfloat16m4_t -reinterpret_f32m4_f16m4 (vfloat32m4_t v) -{ - return __riscv_vreinterpret_v_i16m4_f16m4 ( - __riscv_vreinterpret_v_i32m4_i16m4 (__riscv_vreinterpret_v_f32m4_i32m4 (v))); -} - -DEF_GROUP_OVERLAP_TERNARY_0( - __riscv_vsetvlmax_e16m2, - vfloat16m2_t, - vfloat32m4_t, - __riscv_vle16_v_f16m2, - __riscv_vle32_v_f32m4, - __riscv_vfwmsac_vv_f32m4, - __riscv_vse32_v_f32m4, - vfwmsac_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_X8) - -DEF_GROUP_OVERLAP_TERNARY_1( - __riscv_vsetvlmax_e16m2, - vfloat16m2_t, - vfloat32m4_t, - vfloat16m4_t, - __riscv_vle16_v_f16m2, - __riscv_vle32_v_f32m4, - reinterpret_f32m4_f16m4, - __riscv_vget_v_f16m4_f16m2, - __riscv_vfwmsac_vv_f32m4, - __riscv_vse32_v_f32m4, - vfwmsac_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_OVERLAP_X2) - -/* ternary_0: the accumulator occupies the whole destination register group and - is live when the narrowed sources are read, so no source can be allocated - inside the destination register group. */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v8,v0,v30([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v0,v28,v26([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v28,v24,v22([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v24,v20,v18([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v20,v16,v14([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v16,v12,v10([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v12,v8,v6([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v8,v4,v2([^0-9]|$)} 1 } } */ - -/* ternary_1: each narrowed source is the highest-numbered half of its own - accumulator, thus it overlaps the highest-numbered part of the destination - register group. Without the group overlap the sources would have to be - copied out to a disjoint register group first. */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v8,v10,v16([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v4,v6,v2([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m4.c deleted file mode 100644 index b27941106cd9..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-m4.c +++ /dev/null @@ -1,52 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ - -#include "group_overlap.h" - -static inline vfloat16m8_t -reinterpret_f32m8_f16m8 (vfloat32m8_t v) -{ - return __riscv_vreinterpret_v_i16m8_f16m8 ( - __riscv_vreinterpret_v_i32m8_i16m8 (__riscv_vreinterpret_v_f32m8_i32m8 (v))); -} - -DEF_GROUP_OVERLAP_TERNARY_0( - __riscv_vsetvlmax_e16m4, - vfloat16m4_t, - vfloat32m8_t, - __riscv_vle16_v_f16m4, - __riscv_vle32_v_f32m8, - __riscv_vfwmsac_vv_f32m8, - __riscv_vse32_v_f32m8, - vfwmsac_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_X4) - -DEF_GROUP_OVERLAP_TERNARY_1( - __riscv_vsetvlmax_e16m4, - vfloat16m4_t, - vfloat32m8_t, - vfloat16m8_t, - __riscv_vle16_v_f16m4, - __riscv_vle32_v_f32m8, - reinterpret_f32m8_f16m8, - __riscv_vget_v_f16m8_f16m4, - __riscv_vfwmsac_vv_f32m8, - __riscv_vse32_v_f32m8, - vfwmsac_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_OVERLAP_X2) - -/* ternary_0: the accumulator occupies the whole destination register group and - is live when the narrowed sources are read, so no source can be allocated - inside the destination register group. */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v16,v0,v4([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v0,v28,v20([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v24,v16,v12([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v16,v8,v12([^0-9]|$)} 1 } } */ - -/* ternary_1: each narrowed source is the highest-numbered half of its own - accumulator, thus it overlaps the highest-numbered part of the destination - register group. Without the group overlap the sources would have to be - copied out to a disjoint register group first. */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v16,v20,v0([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v8,v12,v4([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-mf2.c deleted file mode 100644 index 0a32d56aed09..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-mf2.c +++ /dev/null @@ -1,21 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ - -#include "group_overlap.h" - -DEF_GROUP_OVERLAP_TERNARY_0( - __riscv_vsetvlmax_e16m1, - vfloat16mf2_t, - vfloat32m1_t, - __riscv_vle16_v_f16mf2, - __riscv_vle32_v_f32m1, - __riscv_vfwmsac_vv_f32m1, - __riscv_vse32_v_f32m1, - vfwmsac_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_X16) - -/* The fractional LMUL source has EMUL < 1, thus the widened destination - register group must not overlap either source at all. */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv} 16 } } */ -/* { dg-final { scan-assembler-not {vfwmsac\.vv\s+(v[0-9]+),\1,} } } */ -/* { dg-final { scan-assembler-not {vfwmsac\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-mf4.c deleted file mode 100644 index 741275928354..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f16-mf4.c +++ /dev/null @@ -1,21 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d" } */ - -#include "group_overlap.h" - -DEF_GROUP_OVERLAP_TERNARY_0( - __riscv_vsetvlmax_e16m1, - vfloat16mf4_t, - vfloat32mf2_t, - __riscv_vle16_v_f16mf4, - __riscv_vle32_v_f32mf2, - __riscv_vfwmsac_vv_f32mf2, - __riscv_vse32_v_f32mf2, - vfwmsac_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_X16) - -/* The fractional LMUL source has EMUL < 1, thus the widened destination - register group must not overlap either source at all. */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv} 16 } } */ -/* { dg-final { scan-assembler-not {vfwmsac\.vv\s+(v[0-9]+),\1,} } } */ -/* { dg-final { scan-assembler-not {vfwmsac\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m1.c deleted file mode 100644 index 8c0c41ca6bba..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m1.c +++ /dev/null @@ -1,64 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ - -#include "group_overlap.h" - -static inline vfloat32m2_t -reinterpret_f64m2_f32m2 (vfloat64m2_t v) -{ - return __riscv_vreinterpret_v_i32m2_f32m2 ( - __riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (v))); -} - -DEF_GROUP_OVERLAP_TERNARY_0( - __riscv_vsetvlmax_e32m1, - vfloat32m1_t, - vfloat64m2_t, - __riscv_vle32_v_f32m1, - __riscv_vle64_v_f64m2, - __riscv_vfwmsac_vv_f64m2, - __riscv_vse64_v_f64m2, - vfwmsac_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_X16) - -DEF_GROUP_OVERLAP_TERNARY_1( - __riscv_vsetvlmax_e32m1, - vfloat32m1_t, - vfloat64m2_t, - vfloat32m2_t, - __riscv_vle32_v_f32m1, - __riscv_vle64_v_f64m2, - reinterpret_f64m2_f32m2, - __riscv_vget_v_f32m2_f32m1, - __riscv_vfwmsac_vv_f64m2, - __riscv_vse64_v_f64m2, - vfwmsac_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_OVERLAP_X2) - -/* ternary_0: the accumulator occupies the whole destination register group and - is live when the narrowed sources are read, so no source can be allocated - inside the destination register group. */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v12,v30,v29([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v4,v16,v15([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v2,v0,v31([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v8,v14,v1([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v30,v28,v27([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v28,v26,v25([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v6,v20,v19([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v26,v24,v23([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v2,v18,v17([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v10,v1,v15([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v24,v22,v21([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v14,v19,v17([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v16,v21,v23([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v18,v20,v22([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v20,v0,v1([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v22,v0,v1([^0-9]|$)} 1 } } */ - -/* ternary_1: each narrowed source is the highest-numbered half of its own - accumulator, thus it overlaps the highest-numbered part of the destination - register group. Without the group overlap the sources would have to be - copied out to a disjoint register group first. */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v4,v5,v8([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v2,v3,v1([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m2.c deleted file mode 100644 index 3156cc21fd79..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m2.c +++ /dev/null @@ -1,56 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ - -#include "group_overlap.h" - -static inline vfloat32m4_t -reinterpret_f64m4_f32m4 (vfloat64m4_t v) -{ - return __riscv_vreinterpret_v_i32m4_f32m4 ( - __riscv_vreinterpret_v_i64m4_i32m4 (__riscv_vreinterpret_v_f64m4_i64m4 (v))); -} - -DEF_GROUP_OVERLAP_TERNARY_0( - __riscv_vsetvlmax_e32m2, - vfloat32m2_t, - vfloat64m4_t, - __riscv_vle32_v_f32m2, - __riscv_vle64_v_f64m4, - __riscv_vfwmsac_vv_f64m4, - __riscv_vse64_v_f64m4, - vfwmsac_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_X8) - -DEF_GROUP_OVERLAP_TERNARY_1( - __riscv_vsetvlmax_e32m2, - vfloat32m2_t, - vfloat64m4_t, - vfloat32m4_t, - __riscv_vle32_v_f32m2, - __riscv_vle64_v_f64m4, - reinterpret_f64m4_f32m4, - __riscv_vget_v_f32m4_f32m2, - __riscv_vfwmsac_vv_f64m4, - __riscv_vse64_v_f64m4, - vfwmsac_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_OVERLAP_X2) - -/* ternary_0: the accumulator occupies the whole destination register group and - is live when the narrowed sources are read, so no source can be allocated - inside the destination register group. */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v8,v0,v30([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v0,v28,v26([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v28,v24,v22([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v24,v20,v18([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v20,v16,v14([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v16,v12,v10([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v12,v8,v6([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v8,v4,v2([^0-9]|$)} 1 } } */ - -/* ternary_1: each narrowed source is the highest-numbered half of its own - accumulator, thus it overlaps the highest-numbered part of the destination - register group. Without the group overlap the sources would have to be - copied out to a disjoint register group first. */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v8,v10,v16([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v4,v6,v2([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m4.c deleted file mode 100644 index 3c62fda04fd3..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-m4.c +++ /dev/null @@ -1,52 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ - -#include "group_overlap.h" - -static inline vfloat32m8_t -reinterpret_f64m8_f32m8 (vfloat64m8_t v) -{ - return __riscv_vreinterpret_v_i32m8_f32m8 ( - __riscv_vreinterpret_v_i64m8_i32m8 (__riscv_vreinterpret_v_f64m8_i64m8 (v))); -} - -DEF_GROUP_OVERLAP_TERNARY_0( - __riscv_vsetvlmax_e32m4, - vfloat32m4_t, - vfloat64m8_t, - __riscv_vle32_v_f32m4, - __riscv_vle64_v_f64m8, - __riscv_vfwmsac_vv_f64m8, - __riscv_vse64_v_f64m8, - vfwmsac_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_X4) - -DEF_GROUP_OVERLAP_TERNARY_1( - __riscv_vsetvlmax_e32m4, - vfloat32m4_t, - vfloat64m8_t, - vfloat32m8_t, - __riscv_vle32_v_f32m4, - __riscv_vle64_v_f64m8, - reinterpret_f64m8_f32m8, - __riscv_vget_v_f32m8_f32m4, - __riscv_vfwmsac_vv_f64m8, - __riscv_vse64_v_f64m8, - vfwmsac_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_OVERLAP_X2) - -/* ternary_0: the accumulator occupies the whole destination register group and - is live when the narrowed sources are read, so no source can be allocated - inside the destination register group. */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v16,v0,v4([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v0,v28,v20([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v24,v16,v12([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v16,v8,v12([^0-9]|$)} 1 } } */ - -/* ternary_1: each narrowed source is the highest-numbered half of its own - accumulator, thus it overlaps the highest-numbered part of the destination - register group. Without the group overlap the sources would have to be - copied out to a disjoint register group first. */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v16,v20,v0([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv\s+v8,v12,v4([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-mf2.c deleted file mode 100644 index c25f2af6eef0..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vfwmsac_vv-f32-mf2.c +++ /dev/null @@ -1,21 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ - -#include "group_overlap.h" - -DEF_GROUP_OVERLAP_TERNARY_0( - __riscv_vsetvlmax_e32m1, - vfloat32mf2_t, - vfloat64m1_t, - __riscv_vle32_v_f32mf2, - __riscv_vle64_v_f64m1, - __riscv_vfwmsac_vv_f64m1, - __riscv_vse64_v_f64m1, - vfwmsac_vv, - LOOP_DUAL_WIDEN_TERNARY_BODY_X16) - -/* The fractional LMUL source has EMUL < 1, thus the widened destination - register group must not overlap either source at all. */ -/* { dg-final { scan-assembler-times {vfwmsac\.vv} 16 } } */ -/* { dg-final { scan-assembler-not {vfwmsac\.vv\s+(v[0-9]+),\1,} } } */ -/* { dg-final { scan-assembler-not {vfwmsac\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-61.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-61.c deleted file mode 100644 index 74521b728034..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-61.c +++ /dev/null @@ -1,59 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -void -foo (void *in, void *out, int n) -{ - for (int i = 0; i < n; i++) - { - asm volatile("nop" ::: "memory"); - vfloat64m4_t v0 = __riscv_vle64_v_f64m4 (in, 4);in+=100; - vfloat32m2_t v0_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v0, 1)))); - v0 = __riscv_vfwmacc_vv_f64m4_tu (v0, v0_n, v0_n, 4); - asm volatile("nop" ::: "memory"); - vfloat64m4_t v1 = __riscv_vle64_v_f64m4 (in, 4);in+=100; - vfloat32m2_t v1_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v1, 1)))); - v1 = __riscv_vfwmacc_vv_f64m4_tu (v1, v1_n, v1_n, 4); - asm volatile("nop" ::: "memory"); - vfloat64m4_t v2 = __riscv_vle64_v_f64m4 (in, 4);in+=100; - vfloat32m2_t v2_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v2, 1)))); - v2 = __riscv_vfwmacc_vv_f64m4_tu (v2, v2_n, v2_n, 4); - asm volatile("nop" ::: "memory"); - vfloat64m4_t v3 = __riscv_vle64_v_f64m4 (in, 4);in+=100; - vfloat32m2_t v3_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v3, 1)))); - v3 = __riscv_vfwmacc_vv_f64m4_tu (v3, v3_n, v3_n, 4); - asm volatile("nop" ::: "memory"); - vfloat64m4_t v4 = __riscv_vle64_v_f64m4 (in, 4);in+=100; - vfloat32m2_t v4_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v4, 1)))); - v4 = __riscv_vfwmacc_vv_f64m4_tu (v4, v4_n, v4_n, 4); - asm volatile("nop" ::: "memory"); - vfloat64m4_t v5 = __riscv_vle64_v_f64m4 (in, 4);in+=100; - vfloat32m2_t v5_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v5, 1)))); - v5 = __riscv_vfwmacc_vv_f64m4_tu (v5, v5_n, v5_n, 4); - asm volatile("nop" ::: "memory"); - vfloat64m4_t v6 = __riscv_vle64_v_f64m4 (in, 4);in+=100; - vfloat32m2_t v6_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v6, 1)))); - v6 = __riscv_vfwmacc_vv_f64m4_tu (v6, v6_n, v6_n, 4); - asm volatile("nop" ::: "memory"); - vfloat32m2_t v7_n = __riscv_vle32_v_f32m2 (in, 4);in+=100; - vfloat64m4_t v7 = __riscv_vfwcvt_f_f_v_f64m4 (v7_n, 4); - - asm volatile("nop" ::: "memory"); - __riscv_vsse64_v_f64m4 (out, 8, v0, 4);out+=100; - __riscv_vsse64_v_f64m4 (out, 8, v1, 4);out+=100; - __riscv_vsse64_v_f64m4 (out, 8, v2, 4);out+=100; - __riscv_vsse64_v_f64m4 (out, 8, v3, 4);out+=100; - __riscv_vsse64_v_f64m4 (out, 8, v4, 4);out+=100; - __riscv_vsse64_v_f64m4 (out, 8, v5, 4);out+=100; - __riscv_vsse64_v_f64m4 (out, 8, v6, 4);out+=100; - __riscv_vsse64_v_f64m4 (out, 8, v7, 4);out+=100; - } -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-62.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-62.c deleted file mode 100644 index 8c7032cd8756..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-62.c +++ /dev/null @@ -1,59 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -void -foo (void *in, void *out, int n) -{ - for (int i = 0; i < n; i++) - { - asm volatile("nop" ::: "memory"); - vfloat64m4_t v0 = __riscv_vle64_v_f64m4 (in, 4);in+=100; - vfloat32m2_t v0_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v0, 1)))); - v0 = __riscv_vfwmsac_vv_f64m4_tu (v0, v0_n, v0_n, 4); - asm volatile("nop" ::: "memory"); - vfloat64m4_t v1 = __riscv_vle64_v_f64m4 (in, 4);in+=100; - vfloat32m2_t v1_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v1, 1)))); - v1 = __riscv_vfwmsac_vv_f64m4_tu (v1, v1_n, v1_n, 4); - asm volatile("nop" ::: "memory"); - vfloat64m4_t v2 = __riscv_vle64_v_f64m4 (in, 4);in+=100; - vfloat32m2_t v2_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v2, 1)))); - v2 = __riscv_vfwmsac_vv_f64m4_tu (v2, v2_n, v2_n, 4); - asm volatile("nop" ::: "memory"); - vfloat64m4_t v3 = __riscv_vle64_v_f64m4 (in, 4);in+=100; - vfloat32m2_t v3_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v3, 1)))); - v3 = __riscv_vfwmsac_vv_f64m4_tu (v3, v3_n, v3_n, 4); - asm volatile("nop" ::: "memory"); - vfloat64m4_t v4 = __riscv_vle64_v_f64m4 (in, 4);in+=100; - vfloat32m2_t v4_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v4, 1)))); - v4 = __riscv_vfwmsac_vv_f64m4_tu (v4, v4_n, v4_n, 4); - asm volatile("nop" ::: "memory"); - vfloat64m4_t v5 = __riscv_vle64_v_f64m4 (in, 4);in+=100; - vfloat32m2_t v5_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v5, 1)))); - v5 = __riscv_vfwmsac_vv_f64m4_tu (v5, v5_n, v5_n, 4); - asm volatile("nop" ::: "memory"); - vfloat64m4_t v6 = __riscv_vle64_v_f64m4 (in, 4);in+=100; - vfloat32m2_t v6_n = __riscv_vreinterpret_v_i32m2_f32m2 (__riscv_vreinterpret_v_i64m2_i32m2 (__riscv_vreinterpret_v_f64m2_i64m2 (__riscv_vget_v_f64m4_f64m2 (v6, 1)))); - v6 = __riscv_vfwmsac_vv_f64m4_tu (v6, v6_n, v6_n, 4); - asm volatile("nop" ::: "memory"); - vfloat32m2_t v7_n = __riscv_vle32_v_f32m2 (in, 4);in+=100; - vfloat64m4_t v7 = __riscv_vfwcvt_f_f_v_f64m4 (v7_n, 4); - - asm volatile("nop" ::: "memory"); - __riscv_vsse64_v_f64m4 (out, 8, v0, 4);out+=100; - __riscv_vsse64_v_f64m4 (out, 8, v1, 4);out+=100; - __riscv_vsse64_v_f64m4 (out, 8, v2, 4);out+=100; - __riscv_vsse64_v_f64m4 (out, 8, v3, 4);out+=100; - __riscv_vsse64_v_f64m4 (out, 8, v4, 4);out+=100; - __riscv_vsse64_v_f64m4 (out, 8, v5, 4);out+=100; - __riscv_vsse64_v_f64m4 (out, 8, v6, 4);out+=100; - __riscv_vsse64_v_f64m4 (out, 8, v7, 4);out+=100; - } -} - -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */
