https://gcc.gnu.org/g:c3c3977e691a99d0e86d6059d7a4d583f77f89cc
commit r17-5719-gc3c3977e691a99d0e86d6059d7a4d583f77f89cc Author: Pan Li <[email protected]> Date: Wed Oct 28 10:37:29 2026 +0800 RISC-V: Disable RVV register overlap for vwmaccsu.vx [PR target/128162] Revert the register overlap of the widening multiply-add insn vwmaccsu.vx and the related test cases. The insn reads the vd as the accumulator with EEW = 2 * SEW, while the vs1 and vs2 are read with EEW = SEW. The section 5.2 of the vector spec reserves any encoding in which one vector register supplies source operands with two or more different EEWs. Thus, the vs1 and vs2 must not overlap the vd register group, even in the highest-numbered part. For example, below asm dump is reserved as the v3 is read with both the EEW = 32 and the EEW = 16. vwmaccsu.vx v2,a0,v3 # LMUL = 1, SEW = 16 This reverts commit(s): 68ce5148b9b RISC-V: Allow RVV register overlap for vwmaccsu.vx 4a0bb62b2d4 RISC-V: Add test cases for vwmaccsu.vx reg overlap d45a9c006ad RISC-V: Add more test cases for vwmaccsu.vx PR target/128162 gcc/ChangeLog: * config/riscv/vector.md: Revert Wvr constraint to the early clobber vr. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i16-m1.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i16-m2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i16-m4.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i16-mf2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i16-mf4.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i32-m1.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i32-m2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i32-m4.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i32-mf2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i8-m1.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i8-m2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i8-m4.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i8-mf2.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i8-mf4.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i8-mf8.c: Removed. * gcc.target/riscv/rvv/base/pr112431-55.c: Removed. * gcc.target/riscv/rvv/base/pr112431-56.c: Removed. * gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h: Remove test helper macros. Signed-off-by: Pan Li <[email protected]> Diff: --- gcc/config/riscv/vector.md | 18 +++--- .../rvv/autovec/group_overlap/group_overlap.h | 46 --------------- .../rvv/autovec/group_overlap/vwmaccsu_vx-i16-m1.c | 59 ------------------ .../rvv/autovec/group_overlap/vwmaccsu_vx-i16-m2.c | 51 ---------------- .../rvv/autovec/group_overlap/vwmaccsu_vx-i16-m4.c | 47 --------------- .../autovec/group_overlap/vwmaccsu_vx-i16-mf2.c | 21 ------- .../autovec/group_overlap/vwmaccsu_vx-i16-mf4.c | 21 ------- .../rvv/autovec/group_overlap/vwmaccsu_vx-i32-m1.c | 59 ------------------ .../rvv/autovec/group_overlap/vwmaccsu_vx-i32-m2.c | 51 ---------------- .../rvv/autovec/group_overlap/vwmaccsu_vx-i32-m4.c | 47 --------------- .../autovec/group_overlap/vwmaccsu_vx-i32-mf2.c | 21 ------- .../rvv/autovec/group_overlap/vwmaccsu_vx-i8-m1.c | 59 ------------------ .../rvv/autovec/group_overlap/vwmaccsu_vx-i8-m2.c | 51 ---------------- .../rvv/autovec/group_overlap/vwmaccsu_vx-i8-m4.c | 47 --------------- .../rvv/autovec/group_overlap/vwmaccsu_vx-i8-mf2.c | 21 ------- .../rvv/autovec/group_overlap/vwmaccsu_vx-i8-mf4.c | 21 ------- .../rvv/autovec/group_overlap/vwmaccsu_vx-i8-mf8.c | 21 ------- .../gcc.target/riscv/rvv/base/pr112431-55.c | 69 ---------------------- .../gcc.target/riscv/rvv/base/pr112431-56.c | 69 ---------------------- 19 files changed, 9 insertions(+), 790 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 11a9caed8f80..7f7c9e8ddf1b 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -6152,24 +6152,24 @@ (set_attr "mode" "<V_DOUBLE_TRUNC>")]) (define_insn "@pred_widen_mul_plussu<mode>_scalar" - [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vd") + [(set (match_operand:VWEXTI 0 "register_operand" "=&vr") (if_then_else:VWEXTI (unspec:<VM> - [(match_operand:<VM> 1 "vector_mask_operand" "Wc1, vm") - (match_operand 5 "vector_length_operand" "rvl,rvl") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") + [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1") + (match_operand 5 "vector_length_operand" " rvl") + (match_operand 6 "const_int_operand" " i") + (match_operand 7 "const_int_operand" " i") + (match_operand 8 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:VWEXTI (mult:VWEXTI (sign_extend:VWEXTI (vec_duplicate:<V_DOUBLE_TRUNC> - (match_operand:<VSUBEL> 3 "register_operand" " r, r"))) + (match_operand:<VSUBEL> 3 "register_operand" " r"))) (zero_extend:VWEXTI - (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "Wvr,Wvr"))) - (match_operand:VWEXTI 2 "register_operand" " 0, 0")) + (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))) + (match_operand:VWEXTI 2 "register_operand" " 0")) (match_dup 2)))] "TARGET_VECTOR" "vwmaccsu.vx\t%0,%3,%4%p1" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h index 8e3792adcf96..825e12fe4daa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h @@ -1212,34 +1212,6 @@ ST_F ((void *)out, vd0, VL); OUT += VL; \ ST_F ((void *)out, vd1, VL); OUT += VL; \ -/* Like LOOP_DUAL_WIDEN_TERNARY_VX_BODY_OVERLAP_X2 but the narrowed vector - source is unsigned while the accumulator is signed, thus reinterpreting the - accumulator takes two steps: RI_UF turns the signed widened accumulator into - the unsigned widened type, RI_NUF reinterprets that as the unsigned narrowed - element type and GET_UF extracts the highest-numbered half of it. */ -#define LOOP_DUAL_WIDEN_TERNARY_VX_BODY_SU_OVERLAP_X2(NUT, WT, WNUT, LD_WF, \ - RI_UF, RI_NUF, GET_UF,\ - OUT_F, ST_F, OUT, \ - START, X, VL) \ - WT vw0 = LD_WF ((void *)START, VL); START += VL; \ - WT vw1 = LD_WF ((void *)START, VL); START += VL; \ - \ - asm volatile("nop" ::: "memory"); \ - \ - WNUT vr0 = RI_NUF (RI_UF (vw0)); \ - WNUT vr1 = RI_NUF (RI_UF (vw1)); \ - \ - NUT vs0 = GET_UF (vr0, 1); \ - NUT vs1 = GET_UF (vr1, 1); \ - \ - WT vd0 = OUT_F (vw0, X, vs0, VL); \ - WT vd1 = OUT_F (vw1, X, vs1, VL); \ - \ - asm volatile("nop" ::: "memory"); \ - \ - ST_F ((void *)out, vd0, VL); OUT += VL; \ - ST_F ((void *)out, vd1, VL); OUT += VL; \ - /* A widening reduction reads vs1 with EEW = 2 * SEW while vs2 is read with EEW = SEW, thus vs1 must not fall inside the vs2 register group. Taking vs1 out of the vs2 register group itself is the only way the two can be asked to @@ -1463,24 +1435,6 @@ } \ } -#define DEF_GROUP_OVERLAP_TERNARY_6(VL_F, NUT, WT, WNUT, ST, LD_WF, RI_UF, \ - RI_NUF, GET_UF, OUT_F, ST_F, NAME, \ - LOOP_BODY) \ - void test_group_overlap_##NAME##_##NUT##_ternary_6(uint8_t *data, \ - uint8_t *out, \ - ST x, \ - size_t limit) \ - { \ - uint8_t *start = data; \ - uint8_t *end = data + limit; \ - size_t vl = VL_F (); \ - \ - while (start < end) { \ - LOOP_BODY (NUT, WT, WNUT, LD_WF, RI_UF, RI_NUF, GET_UF, OUT_F, ST_F, \ - out, start, x, vl); \ - } \ - } - #define DEF_GROUP_OVERLAP_REDUCE_0(VL_F, NT, WT, WNT, LD_NF, RI_F, GET_F, \ IDX, OUT_F, ST_F, NAME, LOOP_BODY) \ void test_group_overlap_##NAME##_##NT##_reduce_0(uint8_t *data, \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i16-m1.c deleted file mode 100644 index f3359e21dc5e..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i16-m1.c +++ /dev/null @@ -1,59 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ - -#include "group_overlap.h" - -DEF_GROUP_OVERLAP_TERNARY_4( - __riscv_vsetvlmax_e16m1, - vuint16m1_t, - vint32m2_t, - int16_t, - __riscv_vle16_v_u16m1, - __riscv_vle32_v_i32m2, - __riscv_vwmaccsu_vx_i32m2, - __riscv_vse32_v_i32m2, - vwmaccsu_vx, - LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16) - -DEF_GROUP_OVERLAP_TERNARY_6( - __riscv_vsetvlmax_e16m1, - vuint16m1_t, - vint32m2_t, - vuint16m2_t, - int16_t, - __riscv_vle32_v_i32m2, - __riscv_vreinterpret_v_i32m2_u32m2, - __riscv_vreinterpret_v_u32m2_u16m2, - __riscv_vget_v_u16m2_u16m1, - __riscv_vwmaccsu_vx_i32m2, - __riscv_vse32_v_i32m2, - vwmaccsu_vx, - LOOP_DUAL_WIDEN_TERNARY_VX_BODY_SU_OVERLAP_X2) - -/* ternary_4: the accumulator occupies the whole destination register group and - is live when the narrowed source is read, so the source cannot be allocated - inside the destination register group. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v6,s0,v27([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v4,s0,v26([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v26,s0,v24([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v14,s0,v31([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v12,s0,v30([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v2,s0,v25([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v30,s0,v23([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v24,s0,v22([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v10,s0,v29([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v8,s0,v28([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v22,s0,v21([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v26,s0,v20([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v16,s0,v0([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v28,s0,v18([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v20,s0,v19([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v18,s0,v1([^0-9]|$)} 1 } } */ - -/* ternary_6: the narrowed unsigned source is the highest-numbered half of its - own signed accumulator, thus it overlaps the highest-numbered part of the - destination register group. Without the group overlap the source would have - to be copied out to a disjoint register group first. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v4,a2,v5([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v2,a2,v3([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i16-m2.c deleted file mode 100644 index f6f33a91d23d..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i16-m2.c +++ /dev/null @@ -1,51 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ - -#include "group_overlap.h" - -DEF_GROUP_OVERLAP_TERNARY_4( - __riscv_vsetvlmax_e16m2, - vuint16m2_t, - vint32m4_t, - int16_t, - __riscv_vle16_v_u16m2, - __riscv_vle32_v_i32m4, - __riscv_vwmaccsu_vx_i32m4, - __riscv_vse32_v_i32m4, - vwmaccsu_vx, - LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X8) - -DEF_GROUP_OVERLAP_TERNARY_6( - __riscv_vsetvlmax_e16m2, - vuint16m2_t, - vint32m4_t, - vuint16m4_t, - int16_t, - __riscv_vle32_v_i32m4, - __riscv_vreinterpret_v_i32m4_u32m4, - __riscv_vreinterpret_v_u32m4_u16m4, - __riscv_vget_v_u16m4_u16m2, - __riscv_vwmaccsu_vx_i32m4, - __riscv_vse32_v_i32m4, - vwmaccsu_vx, - LOOP_DUAL_WIDEN_TERNARY_VX_BODY_SU_OVERLAP_X2) - -/* ternary_4: the accumulator occupies the whole destination register group and - is live when the narrowed source is read, so the source cannot be allocated - inside the destination register group. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v12,a2,v30([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v8,a2,v28([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v28,a2,v24([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v4,a2,v26([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v16,a2,v0([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v24,a2,v22([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v28,a2,v20([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v20,a2,v2([^0-9]|$)} 1 } } */ - -/* ternary_6: the narrowed unsigned source is the highest-numbered half of its - own signed accumulator, thus it overlaps the highest-numbered part of the - destination register group. Without the group overlap the source would have - to be copied out to a disjoint register group first. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v8,a2,v10([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v4,a2,v6([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i16-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i16-m4.c deleted file mode 100644 index 36900ae86e60..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i16-m4.c +++ /dev/null @@ -1,47 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ - -#include "group_overlap.h" - -DEF_GROUP_OVERLAP_TERNARY_4( - __riscv_vsetvlmax_e16m4, - vuint16m4_t, - vint32m8_t, - int16_t, - __riscv_vle16_v_u16m4, - __riscv_vle32_v_i32m8, - __riscv_vwmaccsu_vx_i32m8, - __riscv_vse32_v_i32m8, - vwmaccsu_vx, - LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X4) - -DEF_GROUP_OVERLAP_TERNARY_6( - __riscv_vsetvlmax_e16m4, - vuint16m4_t, - vint32m8_t, - vuint16m8_t, - int16_t, - __riscv_vle32_v_i32m8, - __riscv_vreinterpret_v_i32m8_u32m8, - __riscv_vreinterpret_v_u32m8_u16m8, - __riscv_vget_v_u16m8_u16m4, - __riscv_vwmaccsu_vx_i32m8, - __riscv_vse32_v_i32m8, - vwmaccsu_vx, - LOOP_DUAL_WIDEN_TERNARY_VX_BODY_SU_OVERLAP_X2) - -/* ternary_4: the accumulator occupies the whole destination register group and - is live when the narrowed source is read, so the source cannot be allocated - inside the destination register group. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v24,a2,v12([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v16,a2,v0([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v16,a2,v8([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v8,a2,v4([^0-9]|$)} 1 } } */ - -/* ternary_6: the narrowed unsigned source is the highest-numbered half of its - own signed accumulator, thus it overlaps the highest-numbered part of the - destination register group. Without the group overlap the source would have - to be copied out to a disjoint register group first. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v16,a2,v20([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v8,a2,v12([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i16-mf2.c deleted file mode 100644 index ddc1284f95ed..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i16-mf2.c +++ /dev/null @@ -1,21 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ - -#include "group_overlap.h" - -DEF_GROUP_OVERLAP_TERNARY_4( - __riscv_vsetvlmax_e16m1, - vuint16mf2_t, - vint32m1_t, - int16_t, - __riscv_vle16_v_u16mf2, - __riscv_vle32_v_i32m1, - __riscv_vwmaccsu_vx_i32m1, - __riscv_vse32_v_i32m1, - vwmaccsu_vx, - LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16) - -/* The fractional LMUL source has EMUL < 1, thus the widened destination - register group must not overlap the source at all. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx} 16 } } */ -/* { dg-final { scan-assembler-not {vwmaccsu\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i16-mf4.c deleted file mode 100644 index 3e470c08f053..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i16-mf4.c +++ /dev/null @@ -1,21 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ - -#include "group_overlap.h" - -DEF_GROUP_OVERLAP_TERNARY_4( - __riscv_vsetvlmax_e16m1, - vuint16mf4_t, - vint32mf2_t, - int16_t, - __riscv_vle16_v_u16mf4, - __riscv_vle32_v_i32mf2, - __riscv_vwmaccsu_vx_i32mf2, - __riscv_vse32_v_i32mf2, - vwmaccsu_vx, - LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16) - -/* The fractional LMUL source has EMUL < 1, thus the widened destination - register group must not overlap the source at all. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx} 16 } } */ -/* { dg-final { scan-assembler-not {vwmaccsu\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i32-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i32-m1.c deleted file mode 100644 index 9d84829fb473..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i32-m1.c +++ /dev/null @@ -1,59 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ - -#include "group_overlap.h" - -DEF_GROUP_OVERLAP_TERNARY_4( - __riscv_vsetvlmax_e32m1, - vuint32m1_t, - vint64m2_t, - int32_t, - __riscv_vle32_v_u32m1, - __riscv_vle64_v_i64m2, - __riscv_vwmaccsu_vx_i64m2, - __riscv_vse64_v_i64m2, - vwmaccsu_vx, - LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16) - -DEF_GROUP_OVERLAP_TERNARY_6( - __riscv_vsetvlmax_e32m1, - vuint32m1_t, - vint64m2_t, - vuint32m2_t, - int32_t, - __riscv_vle64_v_i64m2, - __riscv_vreinterpret_v_i64m2_u64m2, - __riscv_vreinterpret_v_u64m2_u32m2, - __riscv_vget_v_u32m2_u32m1, - __riscv_vwmaccsu_vx_i64m2, - __riscv_vse64_v_i64m2, - vwmaccsu_vx, - LOOP_DUAL_WIDEN_TERNARY_VX_BODY_SU_OVERLAP_X2) - -/* ternary_4: the accumulator occupies the whole destination register group and - is live when the narrowed source is read, so the source cannot be allocated - inside the destination register group. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v6,s0,v27([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v4,s0,v26([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v26,s0,v24([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v14,s0,v31([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v12,s0,v30([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v2,s0,v25([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v30,s0,v23([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v24,s0,v22([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v10,s0,v29([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v8,s0,v28([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v22,s0,v21([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v26,s0,v20([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v16,s0,v0([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v28,s0,v18([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v20,s0,v19([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v18,s0,v1([^0-9]|$)} 1 } } */ - -/* ternary_6: the narrowed unsigned source is the highest-numbered half of its - own signed accumulator, thus it overlaps the highest-numbered part of the - destination register group. Without the group overlap the source would have - to be copied out to a disjoint register group first. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v4,a2,v5([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v2,a2,v3([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i32-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i32-m2.c deleted file mode 100644 index 26f7ee8cb3b4..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i32-m2.c +++ /dev/null @@ -1,51 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ - -#include "group_overlap.h" - -DEF_GROUP_OVERLAP_TERNARY_4( - __riscv_vsetvlmax_e32m2, - vuint32m2_t, - vint64m4_t, - int32_t, - __riscv_vle32_v_u32m2, - __riscv_vle64_v_i64m4, - __riscv_vwmaccsu_vx_i64m4, - __riscv_vse64_v_i64m4, - vwmaccsu_vx, - LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X8) - -DEF_GROUP_OVERLAP_TERNARY_6( - __riscv_vsetvlmax_e32m2, - vuint32m2_t, - vint64m4_t, - vuint32m4_t, - int32_t, - __riscv_vle64_v_i64m4, - __riscv_vreinterpret_v_i64m4_u64m4, - __riscv_vreinterpret_v_u64m4_u32m4, - __riscv_vget_v_u32m4_u32m2, - __riscv_vwmaccsu_vx_i64m4, - __riscv_vse64_v_i64m4, - vwmaccsu_vx, - LOOP_DUAL_WIDEN_TERNARY_VX_BODY_SU_OVERLAP_X2) - -/* ternary_4: the accumulator occupies the whole destination register group and - is live when the narrowed source is read, so the source cannot be allocated - inside the destination register group. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v12,a2,v30([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v8,a2,v28([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v28,a2,v24([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v4,a2,v26([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v16,a2,v0([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v24,a2,v22([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v28,a2,v20([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v20,a2,v2([^0-9]|$)} 1 } } */ - -/* ternary_6: the narrowed unsigned source is the highest-numbered half of its - own signed accumulator, thus it overlaps the highest-numbered part of the - destination register group. Without the group overlap the source would have - to be copied out to a disjoint register group first. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v8,a2,v10([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v4,a2,v6([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i32-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i32-m4.c deleted file mode 100644 index 10c15f953e0d..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i32-m4.c +++ /dev/null @@ -1,47 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ - -#include "group_overlap.h" - -DEF_GROUP_OVERLAP_TERNARY_4( - __riscv_vsetvlmax_e32m4, - vuint32m4_t, - vint64m8_t, - int32_t, - __riscv_vle32_v_u32m4, - __riscv_vle64_v_i64m8, - __riscv_vwmaccsu_vx_i64m8, - __riscv_vse64_v_i64m8, - vwmaccsu_vx, - LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X4) - -DEF_GROUP_OVERLAP_TERNARY_6( - __riscv_vsetvlmax_e32m4, - vuint32m4_t, - vint64m8_t, - vuint32m8_t, - int32_t, - __riscv_vle64_v_i64m8, - __riscv_vreinterpret_v_i64m8_u64m8, - __riscv_vreinterpret_v_u64m8_u32m8, - __riscv_vget_v_u32m8_u32m4, - __riscv_vwmaccsu_vx_i64m8, - __riscv_vse64_v_i64m8, - vwmaccsu_vx, - LOOP_DUAL_WIDEN_TERNARY_VX_BODY_SU_OVERLAP_X2) - -/* ternary_4: the accumulator occupies the whole destination register group and - is live when the narrowed source is read, so the source cannot be allocated - inside the destination register group. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v24,a2,v12([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v16,a2,v0([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v16,a2,v8([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v8,a2,v4([^0-9]|$)} 1 } } */ - -/* ternary_6: the narrowed unsigned source is the highest-numbered half of its - own signed accumulator, thus it overlaps the highest-numbered part of the - destination register group. Without the group overlap the source would have - to be copied out to a disjoint register group first. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v16,a2,v20([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v8,a2,v12([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i32-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i32-mf2.c deleted file mode 100644 index 72e46081d101..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i32-mf2.c +++ /dev/null @@ -1,21 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ - -#include "group_overlap.h" - -DEF_GROUP_OVERLAP_TERNARY_4( - __riscv_vsetvlmax_e32m1, - vuint32mf2_t, - vint64m1_t, - int32_t, - __riscv_vle32_v_u32mf2, - __riscv_vle64_v_i64m1, - __riscv_vwmaccsu_vx_i64m1, - __riscv_vse64_v_i64m1, - vwmaccsu_vx, - LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16) - -/* The fractional LMUL source has EMUL < 1, thus the widened destination - register group must not overlap the source at all. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx} 16 } } */ -/* { dg-final { scan-assembler-not {vwmaccsu\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i8-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i8-m1.c deleted file mode 100644 index b9e7cd44f495..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i8-m1.c +++ /dev/null @@ -1,59 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ - -#include "group_overlap.h" - -DEF_GROUP_OVERLAP_TERNARY_4( - __riscv_vsetvlmax_e8m1, - vuint8m1_t, - vint16m2_t, - int8_t, - __riscv_vle8_v_u8m1, - __riscv_vle16_v_i16m2, - __riscv_vwmaccsu_vx_i16m2, - __riscv_vse16_v_i16m2, - vwmaccsu_vx, - LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16) - -DEF_GROUP_OVERLAP_TERNARY_6( - __riscv_vsetvlmax_e8m1, - vuint8m1_t, - vint16m2_t, - vuint8m2_t, - int8_t, - __riscv_vle16_v_i16m2, - __riscv_vreinterpret_v_i16m2_u16m2, - __riscv_vreinterpret_v_u16m2_u8m2, - __riscv_vget_v_u8m2_u8m1, - __riscv_vwmaccsu_vx_i16m2, - __riscv_vse16_v_i16m2, - vwmaccsu_vx, - LOOP_DUAL_WIDEN_TERNARY_VX_BODY_SU_OVERLAP_X2) - -/* ternary_4: the accumulator occupies the whole destination register group and - is live when the narrowed source is read, so the source cannot be allocated - inside the destination register group. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v6,s0,v27([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v4,s0,v26([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v26,s0,v24([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v14,s0,v31([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v12,s0,v30([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v2,s0,v25([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v30,s0,v23([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v24,s0,v22([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v10,s0,v29([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v8,s0,v28([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v22,s0,v21([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v26,s0,v20([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v16,s0,v0([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v28,s0,v18([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v20,s0,v19([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v18,s0,v1([^0-9]|$)} 1 } } */ - -/* ternary_6: the narrowed unsigned source is the highest-numbered half of its - own signed accumulator, thus it overlaps the highest-numbered part of the - destination register group. Without the group overlap the source would have - to be copied out to a disjoint register group first. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v4,a2,v5([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v2,a2,v3([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i8-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i8-m2.c deleted file mode 100644 index e36f14699b11..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i8-m2.c +++ /dev/null @@ -1,51 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ - -#include "group_overlap.h" - -DEF_GROUP_OVERLAP_TERNARY_4( - __riscv_vsetvlmax_e8m2, - vuint8m2_t, - vint16m4_t, - int8_t, - __riscv_vle8_v_u8m2, - __riscv_vle16_v_i16m4, - __riscv_vwmaccsu_vx_i16m4, - __riscv_vse16_v_i16m4, - vwmaccsu_vx, - LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X8) - -DEF_GROUP_OVERLAP_TERNARY_6( - __riscv_vsetvlmax_e8m2, - vuint8m2_t, - vint16m4_t, - vuint8m4_t, - int8_t, - __riscv_vle16_v_i16m4, - __riscv_vreinterpret_v_i16m4_u16m4, - __riscv_vreinterpret_v_u16m4_u8m4, - __riscv_vget_v_u8m4_u8m2, - __riscv_vwmaccsu_vx_i16m4, - __riscv_vse16_v_i16m4, - vwmaccsu_vx, - LOOP_DUAL_WIDEN_TERNARY_VX_BODY_SU_OVERLAP_X2) - -/* ternary_4: the accumulator occupies the whole destination register group and - is live when the narrowed source is read, so the source cannot be allocated - inside the destination register group. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v12,a2,v30([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v8,a2,v28([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v28,a2,v24([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v4,a2,v26([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v16,a2,v0([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v24,a2,v22([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v28,a2,v20([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v20,a2,v2([^0-9]|$)} 1 } } */ - -/* ternary_6: the narrowed unsigned source is the highest-numbered half of its - own signed accumulator, thus it overlaps the highest-numbered part of the - destination register group. Without the group overlap the source would have - to be copied out to a disjoint register group first. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v8,a2,v10([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v4,a2,v6([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i8-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i8-m4.c deleted file mode 100644 index 1ed83f37cd7d..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i8-m4.c +++ /dev/null @@ -1,47 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ - -#include "group_overlap.h" - -DEF_GROUP_OVERLAP_TERNARY_4( - __riscv_vsetvlmax_e8m4, - vuint8m4_t, - vint16m8_t, - int8_t, - __riscv_vle8_v_u8m4, - __riscv_vle16_v_i16m8, - __riscv_vwmaccsu_vx_i16m8, - __riscv_vse16_v_i16m8, - vwmaccsu_vx, - LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X4) - -DEF_GROUP_OVERLAP_TERNARY_6( - __riscv_vsetvlmax_e8m4, - vuint8m4_t, - vint16m8_t, - vuint8m8_t, - int8_t, - __riscv_vle16_v_i16m8, - __riscv_vreinterpret_v_i16m8_u16m8, - __riscv_vreinterpret_v_u16m8_u8m8, - __riscv_vget_v_u8m8_u8m4, - __riscv_vwmaccsu_vx_i16m8, - __riscv_vse16_v_i16m8, - vwmaccsu_vx, - LOOP_DUAL_WIDEN_TERNARY_VX_BODY_SU_OVERLAP_X2) - -/* ternary_4: the accumulator occupies the whole destination register group and - is live when the narrowed source is read, so the source cannot be allocated - inside the destination register group. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v24,a2,v12([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v16,a2,v0([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v16,a2,v8([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v8,a2,v4([^0-9]|$)} 1 } } */ - -/* ternary_6: the narrowed unsigned source is the highest-numbered half of its - own signed accumulator, thus it overlaps the highest-numbered part of the - destination register group. Without the group overlap the source would have - to be copied out to a disjoint register group first. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v16,a2,v20([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v8,a2,v12([^0-9]|$)} 1 } } */ -/* { dg-final { scan-assembler-not {vmv[0-9]+r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i8-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i8-mf2.c deleted file mode 100644 index 62ee9b1d71da..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i8-mf2.c +++ /dev/null @@ -1,21 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ - -#include "group_overlap.h" - -DEF_GROUP_OVERLAP_TERNARY_4( - __riscv_vsetvlmax_e8m1, - vuint8mf2_t, - vint16m1_t, - int8_t, - __riscv_vle8_v_u8mf2, - __riscv_vle16_v_i16m1, - __riscv_vwmaccsu_vx_i16m1, - __riscv_vse16_v_i16m1, - vwmaccsu_vx, - LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16) - -/* The fractional LMUL source has EMUL < 1, thus the widened destination - register group must not overlap the source at all. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx} 16 } } */ -/* { dg-final { scan-assembler-not {vwmaccsu\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i8-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i8-mf4.c deleted file mode 100644 index 4b583c916ff9..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i8-mf4.c +++ /dev/null @@ -1,21 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ - -#include "group_overlap.h" - -DEF_GROUP_OVERLAP_TERNARY_4( - __riscv_vsetvlmax_e8m1, - vuint8mf4_t, - vint16mf2_t, - int8_t, - __riscv_vle8_v_u8mf4, - __riscv_vle16_v_i16mf2, - __riscv_vwmaccsu_vx_i16mf2, - __riscv_vse16_v_i16mf2, - vwmaccsu_vx, - LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16) - -/* The fractional LMUL source has EMUL < 1, thus the widened destination - register group must not overlap the source at all. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx} 16 } } */ -/* { dg-final { scan-assembler-not {vwmaccsu\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i8-mf8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i8-mf8.c deleted file mode 100644 index 72d84e8877ac..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmaccsu_vx-i8-mf8.c +++ /dev/null @@ -1,21 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ - -#include "group_overlap.h" - -DEF_GROUP_OVERLAP_TERNARY_4( - __riscv_vsetvlmax_e8m1, - vuint8mf8_t, - vint16mf4_t, - int8_t, - __riscv_vle8_v_u8mf8, - __riscv_vle16_v_i16mf4, - __riscv_vwmaccsu_vx_i16mf4, - __riscv_vse16_v_i16mf4, - vwmaccsu_vx, - LOOP_DUAL_WIDEN_TERNARY_VX_BODY_X16) - -/* The fractional LMUL source has EMUL < 1, thus the widened destination - register group must not overlap the source at all. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx} 16 } } */ -/* { dg-final { scan-assembler-not {vwmaccsu\.vx\s+(v[0-9]+),[a-z0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-55.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-55.c deleted file mode 100644 index 47dd71f80921..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-55.c +++ /dev/null @@ -1,69 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -void -foo (void *in, void *out, int n, int8_t x) -{ - for (int i = 0; i < n; i++) - { - asm volatile("nop" ::: "memory"); - vint16m4_t v0 = __riscv_vle16_v_i16m4 (in, 4);in+=100; - vuint16m4_t v0_u = __riscv_vreinterpret_v_i16m4_u16m4 (v0); - vuint8m2_t v0_n = __riscv_vreinterpret_v_u16m2_u8m2 (__riscv_vget_v_u16m4_u16m2 (v0_u, 1)); - v0 = __riscv_vwmaccsu_vx_i16m4_tu (v0, x, v0_n, 4); - asm volatile("nop" ::: "memory"); - vint16m4_t v1 = __riscv_vle16_v_i16m4 (in, 4);in+=100; - vuint16m4_t v1_u = __riscv_vreinterpret_v_i16m4_u16m4 (v1); - vuint8m2_t v1_n = __riscv_vreinterpret_v_u16m2_u8m2 (__riscv_vget_v_u16m4_u16m2 (v1_u, 1)); - v1 = __riscv_vwmaccsu_vx_i16m4_tu (v1, x, v1_n, 4); - asm volatile("nop" ::: "memory"); - vint16m4_t v2 = __riscv_vle16_v_i16m4 (in, 4);in+=100; - vuint16m4_t v2_u = __riscv_vreinterpret_v_i16m4_u16m4 (v2); - vuint8m2_t v2_n = __riscv_vreinterpret_v_u16m2_u8m2 (__riscv_vget_v_u16m4_u16m2 (v2_u, 1)); - v2 = __riscv_vwmaccsu_vx_i16m4_tu (v2, x, v2_n, 4); - asm volatile("nop" ::: "memory"); - vint16m4_t v3 = __riscv_vle16_v_i16m4 (in, 4);in+=100; - vuint16m4_t v3_u = __riscv_vreinterpret_v_i16m4_u16m4 (v3); - vuint8m2_t v3_n = __riscv_vreinterpret_v_u16m2_u8m2 (__riscv_vget_v_u16m4_u16m2 (v3_u, 1)); - v3 = __riscv_vwmaccsu_vx_i16m4_tu (v3, x, v3_n, 4); - asm volatile("nop" ::: "memory"); - vint16m4_t v4 = __riscv_vle16_v_i16m4 (in, 4);in+=100; - vuint16m4_t v4_u = __riscv_vreinterpret_v_i16m4_u16m4 (v4); - vuint8m2_t v4_n = __riscv_vreinterpret_v_u16m2_u8m2 (__riscv_vget_v_u16m4_u16m2 (v4_u, 1)); - v4 = __riscv_vwmaccsu_vx_i16m4_tu (v4, x, v4_n, 4); - asm volatile("nop" ::: "memory"); - vint16m4_t v5 = __riscv_vle16_v_i16m4 (in, 4);in+=100; - vuint16m4_t v5_u = __riscv_vreinterpret_v_i16m4_u16m4 (v5); - vuint8m2_t v5_n = __riscv_vreinterpret_v_u16m2_u8m2 (__riscv_vget_v_u16m4_u16m2 (v5_u, 1)); - v5 = __riscv_vwmaccsu_vx_i16m4_tu (v5, x, v5_n, 4); - asm volatile("nop" ::: "memory"); - vint16m4_t v6 = __riscv_vle16_v_i16m4 (in, 4);in+=100; - vuint16m4_t v6_u = __riscv_vreinterpret_v_i16m4_u16m4 (v6); - vuint8m2_t v6_n = __riscv_vreinterpret_v_u16m2_u8m2 (__riscv_vget_v_u16m4_u16m2 (v6_u, 1)); - v6 = __riscv_vwmaccsu_vx_i16m4_tu (v6, x, v6_n, 4); - asm volatile("nop" ::: "memory"); - vint8m2_t v7_n = __riscv_vle8_v_i8m2 (in, 4);in+=100; - vint16m4_t v7 = __riscv_vwcvt_x_x_v_i16m4 (v7_n, 4); - - asm volatile("nop" ::: "memory"); - __riscv_vsse16_v_i16m4 (out, 4, v0, 4);out+=100; - __riscv_vsse16_v_i16m4 (out, 4, v1, 4);out+=100; - __riscv_vsse16_v_i16m4 (out, 4, v2, 4);out+=100; - __riscv_vsse16_v_i16m4 (out, 4, v3, 4);out+=100; - __riscv_vsse16_v_i16m4 (out, 4, v4, 4);out+=100; - __riscv_vsse16_v_i16m4 (out, 4, v5, 4);out+=100; - __riscv_vsse16_v_i16m4 (out, 4, v6, 4);out+=100; - __riscv_vsse16_v_i16m4 (out, 4, v7, 4);out+=100; - } -} - -/* The narrowed unsigned source is the highest-numbered half of the signed - accumulator, thus it overlaps the destination register group. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v4,[^,]+,v6([^0-9]|$)} 7 } } */ -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-56.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-56.c deleted file mode 100644 index f472cb1152a3..000000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-56.c +++ /dev/null @@ -1,69 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ - -#include "riscv_vector.h" - -void -foo (void *in, void *out, int n, int16_t x) -{ - for (int i = 0; i < n; i++) - { - asm volatile("nop" ::: "memory"); - vint32m4_t v0 = __riscv_vle32_v_i32m4 (in, 4);in+=100; - vuint32m4_t v0_u = __riscv_vreinterpret_v_i32m4_u32m4 (v0); - vuint16m2_t v0_n = __riscv_vreinterpret_v_u32m2_u16m2 (__riscv_vget_v_u32m4_u32m2 (v0_u, 1)); - v0 = __riscv_vwmaccsu_vx_i32m4_tu (v0, x, v0_n, 4); - asm volatile("nop" ::: "memory"); - vint32m4_t v1 = __riscv_vle32_v_i32m4 (in, 4);in+=100; - vuint32m4_t v1_u = __riscv_vreinterpret_v_i32m4_u32m4 (v1); - vuint16m2_t v1_n = __riscv_vreinterpret_v_u32m2_u16m2 (__riscv_vget_v_u32m4_u32m2 (v1_u, 1)); - v1 = __riscv_vwmaccsu_vx_i32m4_tu (v1, x, v1_n, 4); - asm volatile("nop" ::: "memory"); - vint32m4_t v2 = __riscv_vle32_v_i32m4 (in, 4);in+=100; - vuint32m4_t v2_u = __riscv_vreinterpret_v_i32m4_u32m4 (v2); - vuint16m2_t v2_n = __riscv_vreinterpret_v_u32m2_u16m2 (__riscv_vget_v_u32m4_u32m2 (v2_u, 1)); - v2 = __riscv_vwmaccsu_vx_i32m4_tu (v2, x, v2_n, 4); - asm volatile("nop" ::: "memory"); - vint32m4_t v3 = __riscv_vle32_v_i32m4 (in, 4);in+=100; - vuint32m4_t v3_u = __riscv_vreinterpret_v_i32m4_u32m4 (v3); - vuint16m2_t v3_n = __riscv_vreinterpret_v_u32m2_u16m2 (__riscv_vget_v_u32m4_u32m2 (v3_u, 1)); - v3 = __riscv_vwmaccsu_vx_i32m4_tu (v3, x, v3_n, 4); - asm volatile("nop" ::: "memory"); - vint32m4_t v4 = __riscv_vle32_v_i32m4 (in, 4);in+=100; - vuint32m4_t v4_u = __riscv_vreinterpret_v_i32m4_u32m4 (v4); - vuint16m2_t v4_n = __riscv_vreinterpret_v_u32m2_u16m2 (__riscv_vget_v_u32m4_u32m2 (v4_u, 1)); - v4 = __riscv_vwmaccsu_vx_i32m4_tu (v4, x, v4_n, 4); - asm volatile("nop" ::: "memory"); - vint32m4_t v5 = __riscv_vle32_v_i32m4 (in, 4);in+=100; - vuint32m4_t v5_u = __riscv_vreinterpret_v_i32m4_u32m4 (v5); - vuint16m2_t v5_n = __riscv_vreinterpret_v_u32m2_u16m2 (__riscv_vget_v_u32m4_u32m2 (v5_u, 1)); - v5 = __riscv_vwmaccsu_vx_i32m4_tu (v5, x, v5_n, 4); - asm volatile("nop" ::: "memory"); - vint32m4_t v6 = __riscv_vle32_v_i32m4 (in, 4);in+=100; - vuint32m4_t v6_u = __riscv_vreinterpret_v_i32m4_u32m4 (v6); - vuint16m2_t v6_n = __riscv_vreinterpret_v_u32m2_u16m2 (__riscv_vget_v_u32m4_u32m2 (v6_u, 1)); - v6 = __riscv_vwmaccsu_vx_i32m4_tu (v6, x, v6_n, 4); - asm volatile("nop" ::: "memory"); - vint16m2_t v7_n = __riscv_vle16_v_i16m2 (in, 4);in+=100; - vint32m4_t v7 = __riscv_vwcvt_x_x_v_i32m4 (v7_n, 4); - - asm volatile("nop" ::: "memory"); - __riscv_vsse32_v_i32m4 (out, 4, v0, 4);out+=100; - __riscv_vsse32_v_i32m4 (out, 4, v1, 4);out+=100; - __riscv_vsse32_v_i32m4 (out, 4, v2, 4);out+=100; - __riscv_vsse32_v_i32m4 (out, 4, v3, 4);out+=100; - __riscv_vsse32_v_i32m4 (out, 4, v4, 4);out+=100; - __riscv_vsse32_v_i32m4 (out, 4, v5, 4);out+=100; - __riscv_vsse32_v_i32m4 (out, 4, v6, 4);out+=100; - __riscv_vsse32_v_i32m4 (out, 4, v7, 4);out+=100; - } -} - -/* The narrowed unsigned source is the highest-numbered half of the signed - accumulator, thus it overlaps the destination register group. */ -/* { dg-final { scan-assembler-times {vwmaccsu\.vx\s+v4,[^,]+,v6([^0-9]|$)} 7 } } */ -/* { dg-final { scan-assembler-not {vmv1r} } } */ -/* { dg-final { scan-assembler-not {vmv2r} } } */ -/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */ -/* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */
