https://gcc.gnu.org/g:b29929357a409ebdddc1c2eba6cc5a80d279540e
commit b29929357a409ebdddc1c2eba6cc5a80d279540e Author: Michael Meissner <[email protected]> Date: Wed Oct 28 21:14:55 2026 -0400 Revert changes Diff: --- gcc/config/rs6000/fusion.md | 660 ++++++++++++++++------------------------ gcc/config/rs6000/genfusion.pl | 108 +------ gcc/config/rs6000/predicates.md | 12 - gcc/config/rs6000/rs6000.h | 4 - gcc/config/rs6000/rs6000.md | 6 +- 5 files changed, 270 insertions(+), 520 deletions(-) diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md index 9d103600e376..416017149d6f 100644 --- a/gcc/config/rs6000/fusion.md +++ b/gcc/config/rs6000/fusion.md @@ -1871,170 +1871,146 @@ ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vand (define_insn "*fuse_vand_vand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (and:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "%v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vand %3,%3,%2 vand %3,%1,%0\;vand %3,%3,%2 vand %3,%1,%0\;vand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,1\t\t# and (%x2, and (%x0, %x1))) vand %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vand (define_insn "*fuse_vandc_vand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vand %3,%3,%2 vandc %3,%1,%0\;vand %3,%3,%2 vandc %3,%1,%0\;vand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,2\t\t# and (%x2, andc (%x0, %x1))) vandc %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vand (define_insn "*fuse_veqv_vand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;vand %3,%3,%2 veqv %3,%1,%0\;vand %3,%3,%2 veqv %3,%1,%0\;vand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,9\t\t# and (%x2, eqv (%x0, %x1))) veqv %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vand (define_insn "*fuse_vnand_vand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (not:VM (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;vand %3,%3,%2 vnand %3,%1,%0\;vand %3,%3,%2 vnand %3,%1,%0\;vand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,14\t\t# and (%x2, nand (%x0, %x1))) vnand %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vand (define_insn "*fuse_vnor_vand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (not:VM (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;vand %3,%3,%2 vnor %3,%1,%0\;vand %3,%3,%2 vnor %3,%1,%0\;vand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,8\t\t# and (%x2, nor (%x0, %x1))) vnor %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vand (define_insn "*fuse_vor_vand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (ior:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vor %3,%1,%0\;vand %3,%3,%2 vor %3,%1,%0\;vand %3,%3,%2 vor %3,%1,%0\;vand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,7\t\t# and (%x2, or (%x0, %x1))) vor %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vand (define_insn "*fuse_vorc_vand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vand %3,%3,%2 vorc %3,%1,%0\;vand %3,%3,%2 vorc %3,%1,%0\;vand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,11\t\t# and (%x2, orc (%x0, %x1))) vorc %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vand (define_insn "*fuse_vxor_vand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;vand %3,%3,%2 vxor %3,%1,%0\;vand %3,%3,%2 vxor %3,%1,%0\;vand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,6\t\t# and (%x2, xor (%x0, %x1))) vxor %4,%1,%0\;vand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vandc @@ -2057,23 +2033,20 @@ ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vandc (define_insn "*fuse_vandc_vandc" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vandc %3,%3,%2 vandc %3,%1,%0\;vandc %3,%3,%2 vandc %3,%1,%0\;vandc %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,13\t\t# andc (%x2, andc (%x0, %x1))) vandc %4,%1,%0\;vandc %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vandc @@ -2204,23 +2177,20 @@ ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> veqv (define_insn "*fuse_vandc_veqv" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;veqv %3,%3,%2 vandc %3,%1,%0\;veqv %3,%3,%2 vandc %3,%1,%0\;veqv %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,210\t\t# eqv (%x2, andc (%x0, %x1))) vandc %4,%1,%0\;veqv %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> veqv @@ -2297,23 +2267,20 @@ ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> veqv (define_insn "*fuse_vorc_veqv" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;veqv %3,%3,%2 vorc %3,%1,%0\;veqv %3,%3,%2 vorc %3,%1,%0\;veqv %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,75\t\t# eqv (%x2, orc (%x0, %x1))) vorc %4,%1,%0\;veqv %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> veqv @@ -2336,506 +2303,434 @@ ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vnand (define_insn "*fuse_vand_vnand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (not:VM (and:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vnand %3,%3,%2 vand %3,%1,%0\;vnand %3,%3,%2 vand %3,%1,%0\;vnand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,254\t\t# nand (%x2, and (%x0, %x1))) vand %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vnand (define_insn "*fuse_vandc_vnand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vnand %3,%3,%2 vandc %3,%1,%0\;vnand %3,%3,%2 vandc %3,%1,%0\;vnand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,253\t\t# nand (%x2, andc (%x0, %x1))) vandc %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vnand (define_insn "*fuse_veqv_vnand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;vnand %3,%3,%2 veqv %3,%1,%0\;vnand %3,%3,%2 veqv %3,%1,%0\;vnand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,246\t\t# nand (%x2, eqv (%x0, %x1))) veqv %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vnand (define_insn "*fuse_vnand_vnand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (not:VM (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;vnand %3,%3,%2 vnand %3,%1,%0\;vnand %3,%3,%2 vnand %3,%1,%0\;vnand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,241\t\t# nand (%x2, nand (%x0, %x1))) vnand %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vnand (define_insn "*fuse_vnor_vnand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (not:VM (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;vnand %3,%3,%2 vnor %3,%1,%0\;vnand %3,%3,%2 vnor %3,%1,%0\;vnand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,247\t\t# nand (%x2, nor (%x0, %x1))) vnor %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vnand (define_insn "*fuse_vor_vnand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (not:VM (ior:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vor %3,%1,%0\;vnand %3,%3,%2 vor %3,%1,%0\;vnand %3,%3,%2 vor %3,%1,%0\;vnand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,248\t\t# nand (%x2, or (%x0, %x1))) vor %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vnand (define_insn "*fuse_vorc_vnand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vnand %3,%3,%2 vorc %3,%1,%0\;vnand %3,%3,%2 vorc %3,%1,%0\;vnand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,244\t\t# nand (%x2, orc (%x0, %x1))) vorc %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vnand (define_insn "*fuse_vxor_vnand" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;vnand %3,%3,%2 vxor %3,%1,%0\;vnand %3,%3,%2 vxor %3,%1,%0\;vnand %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,249\t\t# nand (%x2, xor (%x0, %x1))) vxor %4,%1,%0\;vnand %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vnor (define_insn "*fuse_vand_vnor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (not:VM (and:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vnor %3,%3,%2 vand %3,%1,%0\;vnor %3,%3,%2 vand %3,%1,%0\;vnor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,224\t\t# nor (%x2, and (%x0, %x1))) vand %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vnor (define_insn "*fuse_vandc_vnor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vnor %3,%3,%2 vandc %3,%1,%0\;vnor %3,%3,%2 vandc %3,%1,%0\;vnor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,208\t\t# nor (%x2, andc (%x0, %x1))) vandc %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vnor (define_insn "*fuse_veqv_vnor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;vnor %3,%3,%2 veqv %3,%1,%0\;vnor %3,%3,%2 veqv %3,%1,%0\;vnor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,96\t\t# nor (%x2, eqv (%x0, %x1))) veqv %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vnor (define_insn "*fuse_vnand_vnor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (not:VM (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;vnor %3,%3,%2 vnand %3,%1,%0\;vnor %3,%3,%2 vnand %3,%1,%0\;vnor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,16\t\t# nor (%x2, nand (%x0, %x1))) vnand %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vnor (define_insn "*fuse_vnor_vnor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (not:VM (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;vnor %3,%3,%2 vnor %3,%1,%0\;vnor %3,%3,%2 vnor %3,%1,%0\;vnor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,112\t\t# nor (%x2, nor (%x0, %x1))) vnor %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vnor (define_insn "*fuse_vor_vnor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (not:VM (ior:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vor %3,%1,%0\;vnor %3,%3,%2 vor %3,%1,%0\;vnor %3,%3,%2 vor %3,%1,%0\;vnor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,128\t\t# nor (%x2, or (%x0, %x1))) vor %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vnor (define_insn "*fuse_vorc_vnor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vnor %3,%3,%2 vorc %3,%1,%0\;vnor %3,%3,%2 vorc %3,%1,%0\;vnor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,64\t\t# nor (%x2, orc (%x0, %x1))) vorc %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vnor (define_insn "*fuse_vxor_vnor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (and:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;vnor %3,%3,%2 vxor %3,%1,%0\;vnor %3,%3,%2 vxor %3,%1,%0\;vnor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,144\t\t# nor (%x2, xor (%x0, %x1))) vxor %4,%1,%0\;vnor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vor (define_insn "*fuse_vand_vor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (and:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vor %3,%3,%2 vand %3,%1,%0\;vor %3,%3,%2 vand %3,%1,%0\;vor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,31\t\t# or (%x2, and (%x0, %x1))) vand %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vor (define_insn "*fuse_vandc_vor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vor %3,%3,%2 vandc %3,%1,%0\;vor %3,%3,%2 vandc %3,%1,%0\;vor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,47\t\t# or (%x2, andc (%x0, %x1))) vandc %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vor (define_insn "*fuse_veqv_vor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;vor %3,%3,%2 veqv %3,%1,%0\;vor %3,%3,%2 veqv %3,%1,%0\;vor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,159\t\t# or (%x2, eqv (%x0, %x1))) veqv %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vor (define_insn "*fuse_vnand_vor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (not:VM (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;vor %3,%3,%2 vnand %3,%1,%0\;vor %3,%3,%2 vnand %3,%1,%0\;vor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,239\t\t# or (%x2, nand (%x0, %x1))) vnand %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vor (define_insn "*fuse_vnor_vor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (not:VM (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;vor %3,%3,%2 vnor %3,%1,%0\;vor %3,%3,%2 vnor %3,%1,%0\;vor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,143\t\t# or (%x2, nor (%x0, %x1))) vnor %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vor (define_insn "*fuse_vor_vor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (ior:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "%v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vor %3,%1,%0\;vor %3,%3,%2 vor %3,%1,%0\;vor %3,%3,%2 vor %3,%1,%0\;vor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,127\t\t# or (%x2, or (%x0, %x1))) vor %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vor (define_insn "*fuse_vorc_vor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vor %3,%3,%2 vorc %3,%1,%0\;vor %3,%3,%2 vorc %3,%1,%0\;vor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,191\t\t# or (%x2, orc (%x0, %x1))) vorc %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vor (define_insn "*fuse_vxor_vor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;vor %3,%3,%2 vxor %3,%1,%0\;vor %3,%3,%2 vxor %3,%1,%0\;vor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,111\t\t# or (%x2, xor (%x0, %x1))) vxor %4,%1,%0\;vor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vorc @@ -2948,23 +2843,20 @@ ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vorc (define_insn "*fuse_vorc_vorc" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (not:VM (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vorc %3,%3,%2 vorc %3,%1,%0\;vorc %3,%3,%2 vorc %3,%1,%0\;vorc %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,79\t\t# orc (%x2, orc (%x0, %x1))) vorc %4,%1,%0\;vorc %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vorc @@ -2987,170 +2879,146 @@ ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vxor (define_insn "*fuse_vand_vxor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (xor:VM (and:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vxor %3,%3,%2 vand %3,%1,%0\;vxor %3,%3,%2 vand %3,%1,%0\;vxor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,30\t\t# xor (%x2, and (%x0, %x1))) vand %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vxor (define_insn "*fuse_vandc_vxor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (xor:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vxor %3,%3,%2 vandc %3,%1,%0\;vxor %3,%3,%2 vandc %3,%1,%0\;vxor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,45\t\t# xor (%x2, andc (%x0, %x1))) vandc %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vxor (define_insn "*fuse_veqv_vxor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (xor:VM (not:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;vxor %3,%3,%2 veqv %3,%1,%0\;vxor %3,%3,%2 veqv %3,%1,%0\;vxor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,150\t\t# xor (%x2, eqv (%x0, %x1))) veqv %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vxor (define_insn "*fuse_vnand_vxor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (xor:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (not:VM (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;vxor %3,%3,%2 vnand %3,%1,%0\;vxor %3,%3,%2 vnand %3,%1,%0\;vxor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,225\t\t# xor (%x2, nand (%x0, %x1))) vnand %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vxor (define_insn "*fuse_vnor_vxor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (xor:VM (and:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (not:VM (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v"))) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;vxor %3,%3,%2 vnor %3,%1,%0\;vxor %3,%3,%2 vnor %3,%1,%0\;vxor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,135\t\t# xor (%x2, nor (%x0, %x1))) vnor %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vxor (define_insn "*fuse_vor_vxor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (xor:VM (ior:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vor %3,%1,%0\;vxor %3,%3,%2 vor %3,%1,%0\;vxor %3,%3,%2 vor %3,%1,%0\;vxor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,120\t\t# xor (%x2, or (%x0, %x1))) vor %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vxor (define_insn "*fuse_vorc_vxor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (xor:VM (ior:VM (not:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 1 "vector_fusion_operand" "v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vxor %3,%3,%2 vorc %3,%1,%0\;vxor %3,%3,%2 vorc %3,%1,%0\;vxor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,180\t\t# xor (%x2, orc (%x0, %x1))) vorc %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vxor (define_insn "*fuse_vxor_vxor" - [(set (match_operand:VM 3 "vector_fusion_operand" "=&0,&1,&v,wa,v") - (xor:VM (xor:VM (match_operand:VM 0 "vector_fusion_operand" "v,v,v,wa,v") - (match_operand:VM 1 "vector_fusion_operand" "%v,v,v,wa,v")) - (match_operand:VM 2 "vector_fusion_operand" "v,v,v,wa,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,X,&v"))] + [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") + (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") + (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) + (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:VM 4 "=X,X,X,&v"))] "(TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;vxor %3,%3,%2 vxor %3,%1,%0\;vxor %3,%3,%2 vxor %3,%1,%0\;vxor %3,%3,%2 - xxeval %x3,%x2,%x1,%x0,105\t\t# xor (%x2, xor (%x0, %x1))) vxor %4,%1,%0\;vxor %3,%4,%2" [(set_attr "type" "fused_vector") (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) + (set_attr "length" "8")]) ;; add-add fusion pattern generated by gen_addadd (define_insn "*fuse_add_add" diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl index a22dbc2982f8..04e6ab15da6e 100755 --- a/gcc/config/rs6000/genfusion.pl +++ b/gcc/config/rs6000/genfusion.pl @@ -211,76 +211,25 @@ sub gen_logical_addsubf $inner_comp, $inner_inv, $inner_rtl, $inner_op, $both_commute, $c4, $bc, $inner_arg0, $inner_arg1, $inner_exp, $outer_arg2, $outer_exp, $ftype, $insn, $is_subf, $is_rsubf, $outer_32, $outer_42,$outer_name, - $fuse_type, $xxeval, $c5, $vect_pred, $vect_inner_arg0, $vect_inner_arg1, - $vect_inner_exp, $vect_outer_arg2, $vect_outer_exp); - - my %xxeval_fusions = ( - "vand_vand" => 1, - "vandc_vand" => 2, - "vxor_vand" => 6, - "vor_vand" => 7, - "vnor_vand" => 8, - "veqv_vand" => 9, - "vorc_vand" => 11, - "vandc_vandc" => 13, - "vnand_vand" => 14, - "vnand_vnor" => 16, - "vand_vxor" => 30, - "vand_vor" => 31, - "vandc_vxor" => 45, - "vandc_vor" => 47, - "vorc_vnor" => 64, - "vorc_veqv" => 75, - "vorc_vorc" => 79, - "veqv_vnor" => 96, - "vxor_vxor" => 105, - "vxor_vor" => 111, - "vnor_vnor" => 112, - "vor_vxor" => 120, - "vor_vor" => 127, - "vor_vnor" => 128, - "vnor_vxor" => 135, - "vnor_vor" => 143, - "vxor_vnor" => 144, - "veqv_vxor" => 150, - "veqv_vor" => 159, - "vorc_vxor" => 180, - "vorc_vor" => 191, - "vandc_vnor" => 208, - "vandc_veqv" => 210, - "vand_vnor" => 224, - "vnand_vxor" => 225, - "vnand_vor" => 239, - "vnand_vnand" => 241, - "vorc_vnand" => 244, - "veqv_vnand" => 246, - "vnor_vnand" => 247, - "vor_vnand" => 248, - "vxor_vnand" => 249, - "vandc_vnand" => 253, - "vand_vnand" => 254, - ); - - KIND: foreach $kind ('scalar','vector') { + $fuse_type); + KIND: foreach $kind ('scalar','vector') { @outer_ops = @logicals; if ( $kind eq 'vector' ) { $vchr = "v"; $mode = "VM"; $pred = "altivec_register_operand"; - $vect_pred = "vector_fusion_operand"; $constraint = "v"; $fuse_type = "fused_vector"; } else { $vchr = ""; $mode = "GPR"; - $vect_pred = $pred = "gpc_reg_operand"; + $pred = "gpc_reg_operand"; $constraint = "r"; $fuse_type = "fused_arith_logical"; push (@outer_ops, @addsub); push (@outer_ops, ( "rsubf" )); } $c4 = "${constraint},${constraint},${constraint},${constraint}"; - $c5 = "${constraint},${constraint},${constraint},wa,${constraint}"; OUTER: foreach $outer ( @outer_ops ) { $outer_name = "${vchr}${outer}"; $is_subf = ( $outer eq "subf" ); @@ -314,33 +263,23 @@ sub gen_logical_addsubf $bc = ""; if ( $both_commute ) { $bc = "%"; } $inner_arg0 = "(match_operand:${mode} 0 \"${pred}\" \"${c4}\")"; $inner_arg1 = "(match_operand:${mode} 1 \"${pred}\" \"${bc}${c4}\")"; - $vect_inner_arg0 = "(match_operand:${mode} 0 \"${vect_pred}\" \"${c5}\")"; - $vect_inner_arg1 = "(match_operand:${mode} 1 \"${vect_pred}\" \"${bc}${c5}\")"; if ( ($inner_comp & 1) == 1 ) { $inner_arg0 = "(not:${mode} $inner_arg0)"; - $vect_inner_arg0 = "(not:${mode} $vect_inner_arg0)"; } if ( ($inner_comp & 2) == 2 ) { $inner_arg1 = "(not:${mode} $inner_arg1)"; - $vect_inner_arg1 = "(not:${mode} $vect_inner_arg1)"; } $inner_exp = "(${inner_rtl}:${mode} ${inner_arg0} ${inner_arg1})"; - $vect_inner_exp = "(${inner_rtl}:${mode} ${vect_inner_arg0} - ${vect_inner_arg1})"; if ( $inner_inv == 1 ) { $inner_exp = "(not:${mode} $inner_exp)"; - $vect_inner_exp = "(not:${mode} $vect_inner_exp)"; } $outer_arg2 = "(match_operand:${mode} 2 \"${pred}\" \"${c4}\")"; - $vect_outer_arg2 = "(match_operand:${mode} 2 \"${vect_pred}\" \"${c5}\")"; if ( ($outer_comp & 1) == 1 ) { $outer_arg2 = "(not:${mode} $outer_arg2)"; - $vect_outer_arg2 = "(not:${mode} $vect_outer_arg2)"; } if ( ($outer_comp & 2) == 2 ) { $inner_exp = "(not:${mode} $inner_exp)"; - $vect_inner_exp = "(not:${mode} $vect_inner_exp)"; } if ( $is_subf ) { $outer_32 = "%2,%3"; @@ -352,23 +291,15 @@ sub gen_logical_addsubf if ( $is_rsubf == 1 ) { $outer_exp = "(${outer_rtl}:${mode} ${outer_arg2} ${inner_exp})"; - $vect_outer_exp = "(${outer_rtl}:${mode} ${vect_outer_arg2} - ${vect_inner_exp})"; } else { $outer_exp = "(${outer_rtl}:${mode} ${inner_exp} ${outer_arg2})"; - $vect_outer_exp = "(${outer_rtl}:${mode} ${vect_inner_exp} - ${vect_outer_arg2})"; } if ( $outer_inv == 1 ) { $outer_exp = "(not:${mode} $outer_exp)"; - $vect_outer_exp = "(not:${mode} $vect_outer_exp)"; } - # See if we can use xxeval on vector fusion - $xxeval = $xxeval_fusions{"${inner_op}_${outer_name}"}; - if (!$xxeval) { - $insn = <<"EOF"; + $insn = <<"EOF"; ;; $ftype fusion pattern generated by gen_logical_addsubf ;; $kind $inner_op -> $outer_name @@ -387,35 +318,6 @@ sub gen_logical_addsubf (set_attr "length" "8")]) EOF - } else { - my ($outer_xxeval) = $outer_op; - my ($inner_xxeval) = $inner_op; - $outer_xxeval =~ s/^v//; - $inner_xxeval =~ s/^v//; - $xxeval .= "\\t\\t# ${outer_xxeval} (%x2, ${inner_xxeval} (%x0, %x1)))"; - $insn = <<"EOF"; - -;; $ftype fusion pattern generated by gen_logical_addsubf -;; $kind $inner_op -> $outer_name -(define_insn "*fuse_${inner_op}_${outer_name}" - [(set (match_operand:${mode} 3 "${vect_pred}" "=&0,&1,&${constraint},wa,${constraint}") - ${vect_outer_exp}) - (clobber (match_scratch:${mode} 4 "=X,X,X,X,&${constraint}"))] - "(TARGET_P10_FUSION)" - "@ - ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32} - ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32} - ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32} - xxeval %x3,%x2,%x1,%x0,${xxeval} - ${inner_op} %4,%1,%0\\;${outer_op} %3,${outer_42}" - [(set_attr "type" "$fuse_type") - (set_attr "cost" "6") - (set_attr "length" "8") - (set_attr "prefixed" "*,*,*,yes,*") - (set_attr "isa" "*,*,*,prefixed,*")]) -EOF - } - print $insn; } } @@ -467,4 +369,4 @@ EOF gen_ld_cmpi_p10(); gen_logical_addsubf(); -gen_addadd(); +gen_addadd; diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 7e028b16a787..b7a0b25921c2 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -119,18 +119,6 @@ return VSX_REGNO_P (REGNO (op)); }) -;; Return 1 if op is a register that can be used for vector fusion. If XXEVAL -;; is supported, return true for all VSX registers, otherwise the fusion is -;; limited to Altivec registers since the machine only fuses Altivec -;; operations. -(define_predicate "vector_fusion_operand" - (match_operand 0 "register_operand") -{ - return (TARGET_XXEVAL - ? vsx_register_operand (op, mode) - : altivec_register_operand (op, mode)); -}) - ;; Return 1 if op is a vector register that operates on floating point vectors ;; (either altivec or VSX). (define_predicate "vfloat_operand" diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index ecd415a9b2f4..0e1ca27b6e60 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -500,10 +500,6 @@ extern int rs6000_vector_align[]; #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ && (TARGET_P9_MINMAX || !flag_trapping_math)) -/* Enable XXEVAL support if we support VSX vector registers and prefixed - instructions to use the xxeval instruction. */ -#define TARGET_XXEVAL (TARGET_VSX && TARGET_PREFIXED) - /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. The MASK_<xxxx> options that have not yet been replaced by their OPTION_MASK_<xxx> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 7c5c0926c22c..5e47b68ad6c3 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -371,7 +371,7 @@ (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) ;; The ISA we implement. -(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10,future,mma,dmf,prefixed" +(define_attr "isa" "any,p5,p6,p7,p7v,p8,p8v,p9,p9v,p9kf,p9tf,p10,future,mma,dmf" (const_string "any")) ;; Is this alternative enabled for the current CPU/ISA/etc.? @@ -436,10 +436,6 @@ (match_test "TARGET_DMF")) (const_int 1) - (and (eq_attr "isa" "prefixed") - (match_test "TARGET_PREFIXED")) - (const_int 1) - ] (const_int 0))) ;; If this instruction is microcoded on the CELL processor
