On Wed, Dec 14, 2016 at 8:04 PM, Andrew Senkevich
<andrew.n.senkev...@gmail.com> wrote:
> here is the second part of k-mask intrinsics, is it Ok?
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -1309,12 +1309,30 @@
> ;; Mask variant shift mnemonics
> (define_code_attr mshift [(ashift "shiftl") (lshiftrt "shiftr")])
>
> +(define_expand "kmovb"
> + [(set (match_operand:QI 0 "nonimmediate_operand")
> + (match_operand:QI 1 "nonimmediate_operand"))]
> + "TARGET_AVX512DQ
> + && !(MEM_P (operands[0]) && MEM_P (operands[1]))")
> +
> (define_expand "kmovw"
> [(set (match_operand:HI 0 "nonimmediate_operand")
> (match_operand:HI 1 "nonimmediate_operand"))]
> "TARGET_AVX512F
> && !(MEM_P (operands[0]) && MEM_P (operands[1]))")
>
> +(define_expand "kmovd"
> + [(set (match_operand:SI 0 "nonimmediate_operand")
> + (match_operand:SI 1 "nonimmediate_operand"))]
> + "TARGET_AVX512BW
> + && !(MEM_P (operands[0]) && MEM_P (operands[1]))")
> +
> +(define_expand "kmovq"
> + [(set (match_operand:DI 0 "nonimmediate_operand")
> + (match_operand:DI 1 "nonimmediate_operand"))]
> + "TARGET_AVX512BW
> + && !(MEM_P (operands[0]) && MEM_P (operands[1]))")
> +
> (define_insn "k<code><mode>"
> [(set (match_operand:SWI1248_AVX512BW 0 "register_operand" "=k")
> (any_logic:SWI1248_AVX512BW
All the above patterns can be macroized with the following patch:
--cut here--
Index: sse.md
===================================================================
--- sse.md (revision 243651)
+++ sse.md (working copy)
@@ -1309,9 +1309,9 @@
;; Mask variant shift mnemonics
(define_code_attr mshift [(ashift "shiftl") (lshiftrt "shiftr")])
-(define_expand "kmovw"
- [(set (match_operand:HI 0 "nonimmediate_operand")
- (match_operand:HI 1 "nonimmediate_operand"))]
+(define_expand "kmov<mskmodesuffix>"
+ [(set (match_operand:SWI1248_AVX512BWDQ 0 "nonimmediate_operand")
+ (match_operand:SWI1248_AVX512BWDQ 1 "nonimmediate_operand"))]
"TARGET_AVX512F
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))")
--cut here--
Please also post ChangeLog entry.
Uros.
