2016-12-15 19:51 GMT+03:00 Uros Bizjak <ubiz...@gmail.com>: > On Thu, Dec 15, 2016 at 2:31 PM, Andrew Senkevich > <andrew.n.senkev...@gmail.com> wrote: >> 2016-12-14 22:55 GMT+03:00 Uros Bizjak <ubiz...@gmail.com>: >>> On Wed, Dec 14, 2016 at 8:04 PM, Andrew Senkevich >>> <andrew.n.senkev...@gmail.com> wrote: >>> >>>> here is the second part of k-mask intrinsics, is it Ok? >>> >>>> --- a/gcc/config/i386/sse.md >>>> +++ b/gcc/config/i386/sse.md >>>> @@ -1309,12 +1309,30 @@ >>>> ;; Mask variant shift mnemonics >>>> (define_code_attr mshift [(ashift "shiftl") (lshiftrt "shiftr")]) >>>> >>>> +(define_expand "kmovb" >>>> + [(set (match_operand:QI 0 "nonimmediate_operand") >>>> + (match_operand:QI 1 "nonimmediate_operand"))] >>>> + "TARGET_AVX512DQ >>>> + && !(MEM_P (operands[0]) && MEM_P (operands[1]))") >>>> + >>>> (define_expand "kmovw" >>>> [(set (match_operand:HI 0 "nonimmediate_operand") >>>> (match_operand:HI 1 "nonimmediate_operand"))] >>>> "TARGET_AVX512F >>>> && !(MEM_P (operands[0]) && MEM_P (operands[1]))") >>>> >>>> +(define_expand "kmovd" >>>> + [(set (match_operand:SI 0 "nonimmediate_operand") >>>> + (match_operand:SI 1 "nonimmediate_operand"))] >>>> + "TARGET_AVX512BW >>>> + && !(MEM_P (operands[0]) && MEM_P (operands[1]))") >>>> + >>>> +(define_expand "kmovq" >>>> + [(set (match_operand:DI 0 "nonimmediate_operand") >>>> + (match_operand:DI 1 "nonimmediate_operand"))] >>>> + "TARGET_AVX512BW >>>> + && !(MEM_P (operands[0]) && MEM_P (operands[1]))") >>>> + >>>> (define_insn "k<code><mode>" >>>> [(set (match_operand:SWI1248_AVX512BW 0 "register_operand" "=k") >>>> (any_logic:SWI1248_AVX512BW >>> >>> All the above patterns can be macroized with the following patch: >>> >>> --cut here-- >>> Index: sse.md >>> =================================================================== >>> --- sse.md (revision 243651) >>> +++ sse.md (working copy) >>> @@ -1309,9 +1309,9 @@ >>> ;; Mask variant shift mnemonics >>> (define_code_attr mshift [(ashift "shiftl") (lshiftrt "shiftr")]) >>> >>> -(define_expand "kmovw" >>> - [(set (match_operand:HI 0 "nonimmediate_operand") >>> - (match_operand:HI 1 "nonimmediate_operand"))] >>> +(define_expand "kmov<mskmodesuffix>" >>> + [(set (match_operand:SWI1248_AVX512BWDQ 0 "nonimmediate_operand") >>> + (match_operand:SWI1248_AVX512BWDQ 1 "nonimmediate_operand"))] >>> "TARGET_AVX512F >>> && !(MEM_P (operands[0]) && MEM_P (operands[1]))") >>> >>> --cut here-- >>> >>> Please also post ChangeLog entry. >> >> Thanks, >> >> here is with ChangeLogs and renamed internal __builtin_ia32_kmov* to >> match instruction names. >> For __builtin_ia32_kmov16 change I will follow up for update in branches. >> >> Regtested on x86_64-linux-gnu, Ok for trunk? > > OK.
Thanks,
here is one more part for kadd{b,w,d,q}, is it ok?
gcc/
* config/i386/avx512bwintrin.h: Add new k-mask intrinsics.
* config/i386/avx512dqintrin.h: Ditto.
* config/i386/avx512fintrin.h: Ditto.
* config/i386/i386-builtin.def (__builtin_ia32_kaddqi,
__builtin_ia32_kaddhi, __builtin_ia32_kaddsi,
__builtin_ia32_kadddi): New.
* config/i386/sse.md (kadd<mode>): New.
gcc/testsuite/
* gcc.target/i386/avx512bw-kaddd-1.c: New test.
* gcc.target/i386/avx512bw-kaddq-1.c: Ditto.
* gcc.target/i386/avx512dq-kaddb-1.c: Ditto.
* gcc.target/i386/avx512f-kaddw-1.c: Ditto.
diff --git a/gcc/config/i386/avx512bwintrin.h b/gcc/config/i386/avx512bwintrin.h
index b35ae2b..e38055c 100644
--- a/gcc/config/i386/avx512bwintrin.h
+++ b/gcc/config/i386/avx512bwintrin.h
@@ -40,6 +40,20 @@ typedef char __v64qi __attribute__ ((__vector_size__ (64)));
typedef unsigned long long __mmask64;
+extern __inline __mmask32
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_kadd_mask32 (__mmask32 __A, __mmask32 __B)
+{
+ return (__mmask32) __builtin_ia32_kaddsi ((__mmask32) __A, (__mmask32) __B);
+}
+
+extern __inline __mmask64
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_kadd_mask64 (__mmask64 __A, __mmask64 __B)
+{
+ return (__mmask64) __builtin_ia32_kadddi ((__mmask64) __A, (__mmask64) __B);
+}
+
extern __inline unsigned int
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_cvtmask32_u32 (__mmask32 __A)
diff --git a/gcc/config/i386/avx512dqintrin.h b/gcc/config/i386/avx512dqintrin.h
index 4db44e4..ccc6a4d 100644
--- a/gcc/config/i386/avx512dqintrin.h
+++ b/gcc/config/i386/avx512dqintrin.h
@@ -34,6 +34,13 @@
#define __DISABLE_AVX512DQ__
#endif /* __AVX512DQ__ */
+extern __inline __mmask8
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_kadd_mask8 (__mmask8 __A, __mmask8 __B)
+{
+ return (__mmask8) __builtin_ia32_kaddqi ((__mmask8) __A, (__mmask8) __B);
+}
+
extern __inline unsigned int
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_cvtmask8_u32 (__mmask8 __A)
diff --git a/gcc/config/i386/avx512fintrin.h b/gcc/config/i386/avx512fintrin.h
index a889c83..820741c 100644
--- a/gcc/config/i386/avx512fintrin.h
+++ b/gcc/config/i386/avx512fintrin.h
@@ -9984,6 +9984,13 @@ _mm512_maskz_expandloadu_epi32 (__mmask16 __U,
void const *__P)
#define _kxnor_mask16 _mm512_kxnor
#define _kxor_mask16 _mm512_kxor
+extern __inline __mmask16
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_kadd_mask16 (__mmask16 __A, __mmask16 __B)
+{
+ return (__mmask16) __builtin_ia32_kaddhi ((__mmask16) __A, (__mmask16) __B);
+}
+
extern __inline unsigned int
__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
_cvtmask16_u32 (__mmask16 __A)
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 71382c8..7d86008 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -1471,6 +1471,10 @@ BDESC (OPTION_MASK_ISA_AVX512DQ,
CODE_FOR_kmovb, "__builtin_ia32_kmovb", IX86_BU
BDESC (OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw,
"__builtin_ia32_kmovw", IX86_BUILTIN_KMOV16, UNKNOWN, (int)
UHI_FTYPE_UHI)
BDESC (OPTION_MASK_ISA_AVX512BW, CODE_FOR_kmovd,
"__builtin_ia32_kmovd", IX86_BUILTIN_KMOV32, UNKNOWN, (int)
USI_FTYPE_USI)
BDESC (OPTION_MASK_ISA_AVX512BW, CODE_FOR_kmovq,
"__builtin_ia32_kmovq", IX86_BUILTIN_KMOV64, UNKNOWN, (int)
UDI_FTYPE_UDI)
+BDESC (OPTION_MASK_ISA_AVX512DQ, CODE_FOR_kaddqi,
"__builtin_ia32_kaddqi", IX86_BUILTIN_KADD8, UNKNOWN, (int)
UQI_FTYPE_UQI_UQI)
+BDESC (OPTION_MASK_ISA_AVX512F, CODE_FOR_kaddhi,
"__builtin_ia32_kaddhi", IX86_BUILTIN_KADD16, UNKNOWN, (int)
UHI_FTYPE_UHI_UHI)
+BDESC (OPTION_MASK_ISA_AVX512BW, CODE_FOR_kaddsi,
"__builtin_ia32_kaddsi", IX86_BUILTIN_KADD32, UNKNOWN, (int)
USI_FTYPE_USI_USI)
+BDESC (OPTION_MASK_ISA_AVX512BW, CODE_FOR_kadddi,
"__builtin_ia32_kadddi", IX86_BUILTIN_KADD64, UNKNOWN, (int)
UDI_FTYPE_UDI_UDI)
/* SHA */
BDESC (OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0,
IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI)
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 6dc57aa..4c9bdec 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -1309,6 +1309,18 @@
;; Mask variant shift mnemonics
(define_code_attr mshift [(ashift "shiftl") (lshiftrt "shiftr")])
+(define_insn "kadd<mode>"
+ [(set (match_operand:SWI1248_AVX512BWDQ 0 "register_operand" "=k")
+ (plus:SWI1248_AVX512BWDQ
+ (match_operand:SWI1248_AVX512BWDQ 1 "register_operand" "k")
+ (match_operand:SWI1248_AVX512BWDQ 2 "register_operand" "k")))
+ (unspec [(const_int 0)] UNSPEC_MASKOP)]
+ "TARGET_AVX512F"
+ "kadd<mskmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "type" "msklog")
+ (set_attr "prefix" "vex")
+ (set_attr "mode" "<MODE>")])
+
(define_expand "kmov<mskmodesuffix>"
[(set (match_operand:SWI1248_AVX512BWDQ 0 "nonimmediate_operand")
(match_operand:SWI1248_AVX512BWDQ 1 "nonimmediate_operand"))]
diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-kaddd-1.c
b/gcc/testsuite/gcc.target/i386/avx512bw-kaddd-1.c
new file mode 100644
index 0000000..1f6c61f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512bw-kaddd-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512bw -O2" } */
+/* { dg-final { scan-assembler-times "kaddd\[
\\t\]+\[^\{\n\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+void
+avx512bw_test ()
+{
+ __mmask32 k = _kadd_mask32 (11, 12);
+ asm volatile ("" : "+k" (k));
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-kaddq-1.c
b/gcc/testsuite/gcc.target/i386/avx512bw-kaddq-1.c
new file mode 100644
index 0000000..9e9aaae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512bw-kaddq-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512bw -O2" } */
+/* { dg-final { scan-assembler-times "kaddq\[
\\t\]+\[^\{\n\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+void
+avx512bw_test ()
+{
+ __mmask64 k = _kadd_mask64 (11, 12);
+ asm volatile ("" : "+k" (k));
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512dq-kaddb-1.c
b/gcc/testsuite/gcc.target/i386/avx512dq-kaddb-1.c
new file mode 100644
index 0000000..4be7b0b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512dq-kaddb-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512dq -O2" } */
+/* { dg-final { scan-assembler-times "kaddb\[
\\t\]+\[^\{\n\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+void
+avx512dq_test ()
+{
+ __mmask8 k = _kadd_mask8 (11, 12);
+ asm volatile ("" : "+k" (k));
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-kaddw-1.c
b/gcc/testsuite/gcc.target/i386/avx512f-kaddw-1.c
new file mode 100644
index 0000000..957a395
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-kaddw-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "kaddw\[
\\t\]+\[^\{\n\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+void
+avx512f_test ()
+{
+ __mmask16 k = _kadd_mask16 (11, 12);
+ asm volatile ("" : "+k" (k));
+}
--
WBR,
Andrew
avx512-kmask-intrin-part3.patch
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