On Thu, Feb 16, 2012 at 5:06 PM, Kirill Yukhin <[email protected]> wrote:
> Hello guys,
> Here is a patch which adds support of first part of Intel TSX extensions.
>
> Could you please have a look?
As the first remark, you don't have to add BLKmode memory clobbers.
unspec_volatile RTX is considered to use and clobber all memory:
+(define_expand "xbegin"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (unspec_volatile:SI [(match_dup 1)] UNSPECV_XBEGIN))]
+ "TARGET_RTM"
+ "operands[1] = force_reg (SImode, constm1_rtx);")
+(define_insn "*xbegin_1"
+ [(set (match_operand:SI 0 "register_operand" "=a")
+ (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "0")]
UNSPECV_XBEGIN))]
+ "TARGET_RTM"
+ "xbegin\t.+6"
+ [(set_attr "type" "other")
+ (set_attr "length" "3")])
But, I think that we want to use code label from the top of the false
branch instead of ".+6". The question is, how to get it ...
+(define_expand "xtest"
+ [(set (match_operand:QI 0 "register_operand" "")
+ (unspec_volatile:QI [(const_int 0)] UNSPECV_XTEST))]
+ "TARGET_RTM"
+{
+ rtx insn, op0, op1;
+ op0 = gen_reg_rtx (QImode);
+ emit_move_insn (op0, const0_rtx);
+ op1 = gen_reg_rtx (QImode);
+ emit_move_insn (op1, const1_rtx);
+ emit_insn (gen_xtest_1 ());
+ insn = gen_rtx_EQ (VOIDmode, gen_rtx_REG (CCZmode, FLAGS_REG),
+ const0_rtx);
+ emit_insn (gen_rtx_SET (VOIDmode, operands[0],
+ gen_rtx_IF_THEN_ELSE (QImode, insn,
+ op1, op0)));
+ DONE;
+})
Please use ix86_expand_setcc instead of opencoding sete insn.
Uros.
