On 8/6/25 00:52, Karl Meakin wrote:
;; Emit a `CBB<cond> (register)` or `CBH<cond> (register)` instruction.
-(define_insn "aarch64_cb<INT_CMP:code><SHORT:mode>"
+(define_insn "*aarch64_cb<INT_CMP:code><SHORT:mode>"
[(set (pc) (if_then_else (INT_CMP
(match_operand:SHORT 0 "register_operand" "r")
(match_operand:SHORT 1 "aarch64_reg_or_zero" "rZ"))
This causes regressions for QI/HImode comparisons (eg the tests in `gcc/testsuite/
gcc.target/aarch64/cmpbr.c`
Yes. I'm less concerned about that than preventing ICE's.
Clearly CBB/CBH support needs to be re-worked.
r~
