From: Pan Li <pan2...@intel.com>

The previous cost value for vec_duplicate almost bases on the operators
like add/minus.  The rtx_cost function try to match them case by case
and find if it has vec_duplicate, then update the cost values.

It is Ok when we initially add it but looks confused/redundant as more
and more operators are involved.  As Robin's suggestion, we only care
about the sub-rtx has vec_duplicate or not, instead of take care of
it by operators.

Thus, this PR would like to refactor that and get rid of the operators
when compute the vec_duplicate cost.

The below test suites are passed for this patch series.
* The rv64gcv fully regression test.

gcc/ChangeLog:

        * config/riscv/riscv.cc (get_vector_binary_rtx_cost): Remove.
        (riscv_rtx_costs): Refactor to serach vec_duplicate on the
        sub rtx.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c: Update
        asm check due to above change.
        * gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c: Ditto.
        * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c: Ditto.
        * gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c: Ditto.
        * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c: Ditto.
        * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c: Ditto.
        * gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c: Ditto.
        * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Ditto.
        * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Ditto.
        * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c: Ditto.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Ditto.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto.

Signed-off-by: Pan Li <pan2...@intel.com>
---
 gcc/config/riscv/riscv.cc                     | 110 ++----------------
 .../rvv/autovec/binop/vadd-rv32gcv-nofm.c     |   4 +-
 .../rvv/autovec/binop/vadd-rv64gcv-nofm.c     |   4 +-
 .../rvv/autovec/binop/vmul-rv32gcv-nofm.c     |   4 +-
 .../rvv/autovec/binop/vmul-rv64gcv-nofm.c     |   4 +-
 .../rvv/autovec/binop/vsub-rv32gcv-nofm.c     |   6 +-
 .../rvv/autovec/binop/vsub-rv64gcv-nofm.c     |   6 +-
 .../rvv/autovec/cond/cond_copysign-rv32gcv.c  |   8 +-
 .../rvv/autovec/cond/cond_copysign-rv64gcv.c  |   8 +-
 .../riscv/rvv/autovec/cond/cond_fadd-1.c      |   4 +-
 .../riscv/rvv/autovec/cond/cond_fadd-2.c      |   4 +-
 .../riscv/rvv/autovec/cond/cond_fadd-3.c      |   4 +-
 .../riscv/rvv/autovec/cond/cond_fadd-4.c      |   4 +-
 .../riscv/rvv/autovec/cond/cond_fma_fnma-1.c  |  12 +-
 .../riscv/rvv/autovec/cond/cond_fma_fnma-3.c  |  12 +-
 .../riscv/rvv/autovec/cond/cond_fma_fnma-4.c  |  12 +-
 .../riscv/rvv/autovec/cond/cond_fma_fnma-5.c  |  12 +-
 .../riscv/rvv/autovec/cond/cond_fma_fnma-6.c  |  12 +-
 .../riscv/rvv/autovec/cond/cond_fmax-1.c      |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmax-2.c      |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmax-3.c      |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmax-4.c      |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmin-1.c      |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmin-2.c      |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmin-3.c      |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmin-4.c      |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c |   4 +-
 .../riscv/rvv/autovec/cond/cond_fms_fnms-1.c  |   4 +-
 .../riscv/rvv/autovec/cond/cond_fms_fnms-3.c  |   4 +-
 .../riscv/rvv/autovec/cond/cond_fms_fnms-4.c  |   4 +-
 .../riscv/rvv/autovec/cond/cond_fms_fnms-5.c  |   4 +-
 .../riscv/rvv/autovec/cond/cond_fms_fnms-6.c  |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmul-1.c      |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmul-2.c      |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmul-3.c      |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmul-4.c      |   4 +-
 .../riscv/rvv/autovec/cond/cond_fmul-5.c      |   4 +-
 .../riscv/rvv/autovec/vx_vf/vf-3-f16.c        |   8 +-
 .../riscv/rvv/autovec/vx_vf/vf-3-f32.c        |   8 +-
 .../riscv/rvv/autovec/vx_vf/vf-3-f64.c        |   8 +-
 .../riscv/rvv/autovec/vx_vf/vx-6-i16.c        |   4 +-
 .../riscv/rvv/autovec/vx_vf/vx-6-i8.c         |   2 +-
 49 files changed, 138 insertions(+), 226 deletions(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e0d8904c1bf..c336584554f 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -3958,41 +3958,6 @@ riscv_extend_cost (rtx op, bool unsigned_p)
   return COSTS_N_INSNS (2);
 }
 
-/* Return the cost of the vector binary rtx like add, minus, mult.
-   The cost of scalar2vr_cost will be appended if there one of the
-   op comes from the VEC_DUPLICATE.  */
-
-static int
-get_vector_binary_rtx_cost (rtx x, int scalar2vr_cost)
-{
-  gcc_assert (riscv_v_ext_mode_p (GET_MODE (x)));
-
-  rtx neg;
-  rtx op_0;
-  rtx op_1;
-
-  if (GET_CODE (x) == UNSPEC)
-    {
-      op_0 = XVECEXP (x, 0, 0);
-      op_1 = XVECEXP (x, 0, 1);
-    }
-  else
-    {
-      op_0 = XEXP (x, 0);
-      op_1 = XEXP (x, 1);
-    }
-
-  if (GET_CODE (op_0) == VEC_DUPLICATE
-      || GET_CODE (op_1) == VEC_DUPLICATE)
-    return (scalar2vr_cost + 1) * COSTS_N_INSNS (1);
-  else if (GET_CODE (neg = op_0) == NEG
-          && (GET_CODE (op_1) == VEC_DUPLICATE
-              || GET_CODE (XEXP (neg, 0)) == VEC_DUPLICATE))
-    return (scalar2vr_cost + 1) * COSTS_N_INSNS (1);
-  else
-    return COSTS_N_INSNS (1);
-}
-
 /* Implement TARGET_RTX_COSTS.  */
 
 #define SINGLE_SHIFT_COST 1
@@ -4014,73 +3979,20 @@ riscv_rtx_costs (rtx x, machine_mode mode, int 
outer_code, int opno ATTRIBUTE_UN
        {
        case SET:
          {
-           switch (GET_CODE (x))
+           if (GET_CODE (x) == VEC_DUPLICATE)
+             *total = (scalar2vr_cost + 1) * COSTS_N_INSNS (1);
+           else
              {
-             case VEC_DUPLICATE:
-               *total = gr2vr_cost * COSTS_N_INSNS (1);
-               break;
-             case IF_THEN_ELSE:
-               {
-                 rtx op = XEXP (x, 1);
+               int vec_dup_count = 0;
+               subrtx_var_iterator::array_type array;
 
-                 switch (GET_CODE (op))
-                   {
-                   case DIV:
-                   case UDIV:
-                   case MOD:
-                   case UMOD:
-                   case US_PLUS:
-                   case US_MINUS:
-                   case SS_PLUS:
-                   case SS_MINUS:
-                     *total = get_vector_binary_rtx_cost (op, scalar2vr_cost);
-                     break;
-                   case UNSPEC:
-                     {
-                       switch (XINT (op, 1))
-                         {
-                         case UNSPEC_VAADDU:
-                         case UNSPEC_VAADD:
-                           *total
-                             = get_vector_binary_rtx_cost (op, scalar2vr_cost);
-                           break;
-                         default:
-                           *total = COSTS_N_INSNS (1);
-                           break;
-                         }
-                     }
-                     break;
-                   default:
-                     *total = COSTS_N_INSNS (1);
-                     break;
-                   }
-               }
-               break;
-             case PLUS:
-             case MINUS:
-             case AND:
-             case IOR:
-             case XOR:
-             case MULT:
-             case SMAX:
-             case UMAX:
-             case SMIN:
-             case UMIN:
-               {
-                 rtx op;
-                 rtx op_0 = XEXP (x, 0);
-                 rtx op_1 = XEXP (x, 1);
+               FOR_EACH_SUBRTX_VAR (iter, array, x, ALL)
+                 if (GET_CODE (*iter) == VEC_DUPLICATE)
+                   vec_dup_count++;
 
-                 if (GET_CODE (op = op_0) == MULT
-                     || GET_CODE (op = op_1) == MULT)
-                   *total = get_vector_binary_rtx_cost (op, scalar2vr_cost);
-                 else
-                   *total = get_vector_binary_rtx_cost (x, scalar2vr_cost);
-               }
-               break;
-             default:
-               *total = COSTS_N_INSNS (1);
-               break;
+               int total_vec_dup_cost = vec_dup_count * scalar2vr_cost;
+
+               *total = COSTS_N_INSNS (1) * (total_vec_dup_cost + 1);
              }
          }
          break;
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
index fab8e79fe72..ca0ea0b16c8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c
@@ -5,7 +5,7 @@
 
 /* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */
 /* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */
-/* { dg-final { scan-assembler-times {\tvfadd\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvfadd\.vf} 6 } } */
+/* { dg-final { scan-assembler-times {\tvfadd\.vv} 9 } } */
+/* { dg-final { scan-assembler-not {\tvfadd\.vf} } } */
 
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 9 "optimized" } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c
index 80bdb683ad0..c839ac7d780 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c
@@ -5,7 +5,7 @@
 
 /* { dg-final { scan-assembler-times {\tvadd\.vv} 16 } } */
 /* { dg-final { scan-assembler-times {\tvadd\.vi} 8 } } */
-/* { dg-final { scan-assembler-times {\tvfadd\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvfadd\.vf} 6 } } */
+/* { dg-final { scan-assembler-times {\tvfadd\.vv} 9 } } */
+/* { dg-final { scan-assembler-not {\tvfadd\.vf} } } */
 
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_ADD" 9 "optimized" } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c
index 7197bf2a385..70f26512e06 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c
@@ -4,6 +4,6 @@
 #include "vmul-template.h"
 
 /* { dg-final { scan-assembler-times {\tvmul\.vv} 16 } } */
-/* { dg-final { scan-assembler-times {\tvfmul\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvfmul\.vf} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfmul\.vv} 6 } } */
+/* { dg-final { scan-assembler-not {\tvfmul\.vf} } } */
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_MUL" 6 "optimized" } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c
index a9c7f9be274..01eb7e7012a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c
@@ -4,6 +4,6 @@
 #include "vmul-template.h"
 
 /* { dg-final { scan-assembler-times {\tvmul\.vv} 16 } } */
-/* { dg-final { scan-assembler-times {\tvfmul\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvfmul\.vf} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfmul\.vv} 6 } } */
+/* { dg-final { scan-assembler-not {\tvfmul\.vf} } } */
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_MUL" 6 "optimized" } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c
index 28b923599ea..c57ac805372 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c
@@ -6,9 +6,9 @@
 /* { dg-final { scan-assembler-times {\tvsub\.vv} 16 } } */
 /* { dg-final { scan-assembler-times {\tvrsub\.vi} 16 } } */
 
-/* { dg-final { scan-assembler-times {\tvfsub\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvfsub\.vf} 3 } } */
-/* { dg-final { scan-assembler-times {\tvfrsub\.vf} 6 } } */
+/* { dg-final { scan-assembler-times {\tvfsub\.vv} 12 } } */
+/* { dg-final { scan-assembler-not {\tvfsub\.vf} } } */
+/* { dg-final { scan-assembler-not {\tvfrsub\.vf} } } */
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 12 "optimized" } } */
 
 /* Do not expect vfrsub for now, because we do not properly
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c
index b0489493b04..a79d7270d88 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c
@@ -6,9 +6,9 @@
 /* { dg-final { scan-assembler-times {\tvsub\.vv} 16 } } */
 /* { dg-final { scan-assembler-times {\tvrsub\.vi} 16 } } */
 
-/* { dg-final { scan-assembler-times {\tvfsub\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvfsub\.vf} 3 } } */
-/* { dg-final { scan-assembler-times {\tvfrsub\.vf} 6 } } */
+/* { dg-final { scan-assembler-times {\tvfsub\.vv} 12 } } */
+/* { dg-final { scan-assembler-not {\tvfsub\.vf} } } */
+/* { dg-final { scan-assembler-not {\tvfrsub\.vf} } } */
 /* { dg-final { scan-tree-dump-times "\.COND_LEN_SUB" 12 "optimized" } } */
 
 /* Do not expect vfrsub for now, because we do not properly
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c
index b9cfc238c73..850679e4292 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c
@@ -3,13 +3,13 @@
 
 #include "cond_copysign-template.h"
 
-/* { dg-final { scan-assembler-times {\tvfsgnj\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvfsgnj\.vf} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfsgnj\.vv} 6 } } */
+/* { dg-final { scan-assembler-not {\tvfsgnj\.vf} } } */
 /* 1. The vectorizer wraps scalar variants of copysign into vector constants 
which
       expand cannot handle currently.
    2. match.pd convert .COPYSIGN (1, b) + COND_MUL to AND + XOR currently.  */
 /* { dg-final { scan-assembler-times {\tvfsgnjx\.vv} 6 { xfail riscv*-*-* } } 
} */
-/* { dg-final { scan-assembler-times {\tvfsgnjn\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvfsgnjn\.vf} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfsgnjn\.vv} 6 } } */
+/* { dg-final { scan-assembler-not {\tvfsgnjn\.vf} } } */
 /* { dg-final { scan-assembler-not {\tvmerge\.vvm} } } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c
index f9f63ebdbbb..84c6c45352f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c
@@ -3,13 +3,13 @@
 
 #include "cond_copysign-template.h"
 
-/* { dg-final { scan-assembler-times {\tvfsgnj\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvfsgnj\.vf} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfsgnj\.vv} 6 } } */
+/* { dg-final { scan-assembler-not {\tvfsgnj\.vf} } } */
 /* 1. The vectorizer wraps scalar variants of copysign into vector constants 
which
       expand cannot handle currently.
    2. match.pd convert .COPYSIGN (1, b) + COND_MUL to AND + XOR currently.  */
 /* { dg-final { scan-assembler-times {\tvfsgnjx\.vv} 6 { xfail riscv*-*-* } } 
} */
-/* { dg-final { scan-assembler-times {\tvfsgnjn\.vv} 3 } } */
-/* { dg-final { scan-assembler-times {\tvfsgnjn\.vf} 3 } } */
+/* { dg-final { scan-assembler-times {\tvfsgnjn\.vv} 6 } } */
+/* { dg-final { scan-assembler-not {\tvfsgnjn\.vf} } } */
 /* { dg-final { scan-assembler-not {\tvmerge\.vvm} } } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c
index 1aac30659f2..02dc6b80ca7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c
@@ -29,6 +29,6 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times 
{vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */
-/* { dg-final { scan-assembler-times 
{vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 18 } } */
+/* { dg-final { scan-assembler-times 
{vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 18 } } */
+/* { dg-final { scan-assembler-not {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c
index 947e43ccde2..7adedf9b729 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c
@@ -28,6 +28,6 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times 
{vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */
-/* { dg-final { scan-assembler-times 
{vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 12 } } */
+/* { dg-final { scan-assembler-times 
{vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 12 } } */
+/* { dg-final { scan-assembler-not {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c
index 8a8d7d03a42..d414f21a255 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c
@@ -29,6 +29,6 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times 
{vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */
-/* { dg-final { scan-assembler-times 
{vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 18 } } */
+/* { dg-final { scan-assembler-times 
{vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 18  } } */
+/* { dg-final { scan-assembler-not {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c
index e282d2c2edc..97d74154e44 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c
@@ -29,6 +29,6 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times 
{vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */
-/* { dg-final { scan-assembler-times 
{vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 18 } } */
+/* { dg-final { scan-assembler-times 
{vfadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 18  } } */
+/* { dg-final { scan-assembler-not {vfadd\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c
index ef8631dd2ed..faee13b3ab4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c
@@ -29,11 +29,11 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times 
{vmadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */
-/* { dg-final { scan-assembler-times 
{vmadd\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */
-/* { dg-final { scan-assembler-times 
{vnmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */
-/* { dg-final { scan-assembler-times 
{vnmsub\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */
-/* { dg-final { scan-assembler-times 
{vfmadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */
-/* { dg-final { scan-assembler-times 
{vfmadd\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-times 
{vmadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-not 
{vmadd\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */
+/* { dg-final { scan-assembler-times 
{vnmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-not 
{vnmsub\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */
+/* { dg-final { scan-assembler-times 
{vfmadd\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {vfmadd\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 
} } */
 /* { dg-final { scan-assembler-times 
{vfnmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c
index e3aaba2c921..1ea22fa5418 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c
@@ -29,11 +29,11 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times 
{vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */
-/* { dg-final { scan-assembler-times 
{vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */
-/* { dg-final { scan-assembler-times 
{vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */
-/* { dg-final { scan-assembler-times 
{vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */
-/* { dg-final { scan-assembler-times 
{vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */
-/* { dg-final { scan-assembler-times 
{vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-times 
{vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-not 
{vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */
+/* { dg-final { scan-assembler-times 
{vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-not 
{vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */
+/* { dg-final { scan-assembler-times 
{vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 
} } */
 /* { dg-final { scan-assembler-times 
{vfnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c
index f91bec12eac..a4870237bc6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c
@@ -29,11 +29,11 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times 
{vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */
-/* { dg-final { scan-assembler-times 
{vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */
-/* { dg-final { scan-assembler-times 
{vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */
-/* { dg-final { scan-assembler-times 
{vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */
-/* { dg-final { scan-assembler-times 
{vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */
-/* { dg-final { scan-assembler-times 
{vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-times 
{vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-not 
{vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */
+/* { dg-final { scan-assembler-times 
{vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-not 
{vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */
+/* { dg-final { scan-assembler-times 
{vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 
} } */
 /* { dg-final { scan-assembler-times 
{vfnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
 /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c
index 381d40532e6..3f2689f57b0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c
@@ -28,12 +28,12 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times 
{vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */
-/* { dg-final { scan-assembler-times 
{vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */
-/* { dg-final { scan-assembler-times 
{vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */
-/* { dg-final { scan-assembler-times 
{vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */
-/* { dg-final { scan-assembler-times 
{vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */
-/* { dg-final { scan-assembler-times 
{vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-times 
{vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-not 
{vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */
+/* { dg-final { scan-assembler-times 
{vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-not 
{vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */
+/* { dg-final { scan-assembler-times 
{vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 
} } */
 /* { dg-final { scan-assembler-times 
{vfnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
 /* NOTE: 14 vmerge is need for other purpose.  */
 /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c
index cb878167619..da20ad818f8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c
@@ -29,12 +29,12 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times 
{vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */
-/* { dg-final { scan-assembler-times 
{vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */
-/* { dg-final { scan-assembler-times 
{vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */
-/* { dg-final { scan-assembler-times 
{vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} 3 } } */
-/* { dg-final { scan-assembler-times 
{vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */
-/* { dg-final { scan-assembler-times 
{vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-times 
{vmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-not 
{vmacc\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */
+/* { dg-final { scan-assembler-times 
{vnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 4 } } */
+/* { dg-final { scan-assembler-not 
{vnmsac\.vx\s+v[0-9]+,[a-x][0-9]+,v[0-9]+,v0.t} } } */
+/* { dg-final { scan-assembler-times 
{vfmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {vfmacc\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 
} } */
 /* { dg-final { scan-assembler-times 
{vfnmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
 /* NOTE: 14 vmerge is need for other purpose.  */
 /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 14 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c
index 95368ad38d1..d34c190cd2a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c
@@ -29,6 +29,6 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times 
{vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */
-/* { dg-final { scan-assembler-times 
{vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */
+/* { dg-final { scan-assembler-times 
{vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
+/* { dg-final { scan-assembler-not {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c
index c07b331d169..b9db723db6f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c
@@ -29,6 +29,6 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times 
{vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */
-/* { dg-final { scan-assembler-times 
{vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */
+/* { dg-final { scan-assembler-times 
{vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
+/* { dg-final { scan-assembler-not {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c
index a01ba8db5b2..473689c2266 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c
@@ -29,6 +29,6 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times 
{vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */
-/* { dg-final { scan-assembler-times 
{vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */
+/* { dg-final { scan-assembler-times 
{vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
+/* { dg-final { scan-assembler-not {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c
index 9aabfb51d72..e41af4288f1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c
@@ -29,6 +29,6 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times 
{vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */
-/* { dg-final { scan-assembler-times 
{vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */
+/* { dg-final { scan-assembler-times 
{vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
+/* { dg-final { scan-assembler-not {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c
index a050d04332a..720eb165d0b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c
@@ -28,6 +28,6 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times 
{vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */
-/* { dg-final { scan-assembler-times 
{vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */
+/* { dg-final { scan-assembler-times 
{vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c
index d251430d057..684d3aa54d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c
@@ -28,6 +28,6 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times 
{vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */
-/* { dg-final { scan-assembler-times 
{vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */
+/* { dg-final { scan-assembler-times 
{vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c
index 790ba2d279a..727b3e35d74 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c
@@ -28,6 +28,6 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times 
{vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */
-/* { dg-final { scan-assembler-times 
{vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */
+/* { dg-final { scan-assembler-times 
{vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c
index 684ae8732f8..e62d9c543ef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c
@@ -28,6 +28,6 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times 
{vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */
-/* { dg-final { scan-assembler-times 
{vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */
+/* { dg-final { scan-assembler-times 
{vfmax\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {vfmax\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c
index 116131b009e..b693f0c62ec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c
@@ -6,6 +6,6 @@
 #define FN(X) __builtin_fmin##X
 #include "cond_fmax-1.c"
 
-/* { dg-final { scan-assembler-times 
{vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */
-/* { dg-final { scan-assembler-times 
{vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */
+/* { dg-final { scan-assembler-times 
{vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
+/* { dg-final { scan-assembler-not {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c
index 6ac47cb0ab9..f504fb1a46c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c
@@ -6,6 +6,6 @@
 #define FN(X) __builtin_fmin##X
 #include "cond_fmax-2.c"
 
-/* { dg-final { scan-assembler-times 
{vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */
-/* { dg-final { scan-assembler-times 
{vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */
+/* { dg-final { scan-assembler-times 
{vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
+/* { dg-final { scan-assembler-not {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c
index 2d445a9224d..d20c833fe3a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c
@@ -6,6 +6,6 @@
 #define FN(X) __builtin_fmin##X
 #include "cond_fmax-3.c"
 
-/* { dg-final { scan-assembler-times 
{vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */
-/* { dg-final { scan-assembler-times 
{vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */
+/* { dg-final { scan-assembler-times 
{vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
+/* { dg-final { scan-assembler-not {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c
index ae642061c38..be4dc337c61 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c
@@ -6,6 +6,6 @@
 #define FN(X) __builtin_fmin##X
 #include "cond_fmax-4.c"
 
-/* { dg-final { scan-assembler-times 
{vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 2 } } */
-/* { dg-final { scan-assembler-times 
{vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 4 } } */
+/* { dg-final { scan-assembler-times 
{vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
+/* { dg-final { scan-assembler-not {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c
index ad4dd9d748d..530fe006960 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c
@@ -6,6 +6,6 @@
 #define FN(X) __builtin_fmin##X
 #include "cond_fmax_zvfh-1.c"
 
-/* { dg-final { scan-assembler-times 
{vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */
-/* { dg-final { scan-assembler-times 
{vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */
+/* { dg-final { scan-assembler-times 
{vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c
index f7fbf227ef3..4ee5c654944 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c
@@ -6,6 +6,6 @@
 #define FN(X) __builtin_fmin##X
 #include "cond_fmax_zvfh-2.c"
 
-/* { dg-final { scan-assembler-times 
{vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */
-/* { dg-final { scan-assembler-times 
{vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */
+/* { dg-final { scan-assembler-times 
{vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c
index 7af181fa887..c44a4624b87 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c
@@ -6,6 +6,6 @@
 #define FN(X) __builtin_fmin##X
 #include "cond_fmax_zvfh-3.c"
 
-/* { dg-final { scan-assembler-times 
{vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */
-/* { dg-final { scan-assembler-times 
{vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */
+/* { dg-final { scan-assembler-times 
{vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c
index 22ff91be383..693d63d4a30 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c
@@ -6,6 +6,6 @@
 #define FN(X) __builtin_fmin##X
 #include "cond_fmax_zvfh-4.c"
 
-/* { dg-final { scan-assembler-times 
{vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 1 } } */
-/* { dg-final { scan-assembler-times 
{vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 2 } } */
+/* { dg-final { scan-assembler-times 
{vfmin\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {vfmin\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c
index 1e367b324da..82a9ea2c5ba 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c
@@ -26,6 +26,6 @@
 TEST_ALL (DEF_LOOP)
 
 /* { dg-final { scan-assembler-times 
{vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */
-/* { dg-final { scan-assembler-times 
{vfmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */
-/* { dg-final { scan-assembler-times 
{vfmsub\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-times 
{vfmsub\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {vfmsub\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c
index 3af559dd7ef..eadeeb8082f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c
@@ -26,6 +26,6 @@
 TEST_ALL (DEF_LOOP)
 
 /* { dg-final { scan-assembler-times 
{vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */
-/* { dg-final { scan-assembler-times 
{vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */
-/* { dg-final { scan-assembler-times 
{vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-times 
{vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c
index e777c8c4755..f00d5f6a921 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c
@@ -26,7 +26,7 @@
 TEST_ALL (DEF_LOOP)
 
 /* { dg-final { scan-assembler-times 
{vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */
-/* { dg-final { scan-assembler-times 
{vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */
-/* { dg-final { scan-assembler-times 
{vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-times 
{vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 
} } */
 /* NOTE: 3 vmerge is need for other purpose.  */
 /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c
index e777c8c4755..f00d5f6a921 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c
@@ -26,7 +26,7 @@
 TEST_ALL (DEF_LOOP)
 
 /* { dg-final { scan-assembler-times 
{vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */
-/* { dg-final { scan-assembler-times 
{vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */
-/* { dg-final { scan-assembler-times 
{vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-times 
{vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 
} } */
 /* NOTE: 3 vmerge is need for other purpose.  */
 /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c
index 46f2b5ff264..6303f416aad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c
@@ -26,7 +26,7 @@
 TEST_ALL (DEF_LOOP)
 
 /* { dg-final { scan-assembler-times 
{vfnmacc\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 { xfail riscv*-*-* } } } */
-/* { dg-final { scan-assembler-times 
{vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */
-/* { dg-final { scan-assembler-times 
{vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-times 
{vfmsac\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 3 } } */
+/* { dg-final { scan-assembler-not {vfmsac\.vf\s+v[0-9]+,fa[0-9],v[0-9]+,v0.t} 
} } */
 /* NOTE: 3 vmerge is need for other purpose.  */
 /* { dg-final { scan-assembler-times {\tvf?merge\.v[vxi]m\t} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c
index 0f85dfc4fdc..1447f40dca7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c
@@ -26,6 +26,6 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times 
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */
-/* { dg-final { scan-assembler-times 
{vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 9 } } */
+/* { dg-final { scan-assembler-times 
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-not {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c
index 6cdb2c40d85..6bc03a0a228 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c
@@ -25,6 +25,6 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times 
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */
-/* { dg-final { scan-assembler-times 
{vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 6 } } */
+/* { dg-final { scan-assembler-times 
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 6 } } */
+/* { dg-final { scan-assembler-not {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c
index 5a921cb614a..c1c2d4e6bc7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c
@@ -26,6 +26,6 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times 
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */
-/* { dg-final { scan-assembler-times 
{vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 9 } } */
+/* { dg-final { scan-assembler-times 
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-not {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c
index 939e6bd8f7f..e9edd23edae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c
@@ -26,6 +26,6 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times 
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */
-/* { dg-final { scan-assembler-times 
{vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 9 } } */
+/* { dg-final { scan-assembler-times 
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-not {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c
index 608fbef7ba9..ccfb651064e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c
@@ -25,6 +25,6 @@
 
 TEST_ALL (DEF_LOOP)
 
-/* { dg-final { scan-assembler-times 
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 0 } } */
-/* { dg-final { scan-assembler-times 
{vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 9 } } */
+/* { dg-final { scan-assembler-times 
{vfmul\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+,v0.t} 9 } } */
+/* { dg-final { scan-assembler-not {vfmul\.vf\s+v[0-9]+,v[0-9]+,fa[0-9],v0.t} 
} } */
 /* { dg-final { scan-assembler-not {\tvf?merge\.v[vxi]m\t} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
index 58afaa4aef9..d50f376c1f2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
@@ -3,10 +3,10 @@
 
 #include "vf_mulop.h"
 
-DEF_VF_MULOP_CASE_1 (_Float16, +, +, add, VF_MULOP_BODY_X16)
-DEF_VF_MULOP_CASE_1 (_Float16, -, +, sub, VF_MULOP_BODY_X16)
-DEF_VF_MULOP_CASE_1 (_Float16, +, -, nadd, VF_MULOP_BODY_X16)
-DEF_VF_MULOP_CASE_1 (_Float16, -, -, nsub, VF_MULOP_BODY_X16)
+DEF_VF_MULOP_CASE_1 (_Float16, +, +, add, VF_MULOP_BODY_X128)
+DEF_VF_MULOP_CASE_1 (_Float16, -, +, sub, VF_MULOP_BODY_X128)
+DEF_VF_MULOP_CASE_1 (_Float16, +, -, nadd, VF_MULOP_BODY_X128)
+DEF_VF_MULOP_CASE_1 (_Float16, -, -, nsub, VF_MULOP_BODY_X128)
 DEF_VF_MULOP_ACC_CASE_1 (_Float16, +, +, acc, VF_MULOP_ACC_BODY_X128)
 DEF_VF_MULOP_ACC_CASE_1 (_Float16, -, +, sac, VF_MULOP_ACC_BODY_X128)
 DEF_VF_MULOP_ACC_CASE_1 (_Float16, +, -, nacc, VF_MULOP_ACC_BODY_X128)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
index 0e95774a489..fe68d6ea017 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
@@ -3,10 +3,10 @@
 
 #include "vf_mulop.h"
 
-DEF_VF_MULOP_CASE_1 (float, +, +, add, VF_MULOP_BODY_X16)
-DEF_VF_MULOP_CASE_1 (float, -, +, sub, VF_MULOP_BODY_X16)
-DEF_VF_MULOP_CASE_1 (float, +, -, nadd, VF_MULOP_BODY_X16)
-DEF_VF_MULOP_CASE_1 (float, -, -, nsub, VF_MULOP_BODY_X16)
+DEF_VF_MULOP_CASE_1 (float, +, +, add, VF_MULOP_BODY_X128)
+DEF_VF_MULOP_CASE_1 (float, -, +, sub, VF_MULOP_BODY_X128)
+DEF_VF_MULOP_CASE_1 (float, +, -, nadd, VF_MULOP_BODY_X128)
+DEF_VF_MULOP_CASE_1 (float, -, -, nsub, VF_MULOP_BODY_X128)
 DEF_VF_MULOP_ACC_CASE_1 (float, +, +, acc, VF_MULOP_ACC_BODY_X128)
 DEF_VF_MULOP_ACC_CASE_1 (float, -, +, sac, VF_MULOP_ACC_BODY_X128)
 DEF_VF_MULOP_ACC_CASE_1 (float, +, -, nacc, VF_MULOP_ACC_BODY_X128)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
index 71bd7e1b957..0b83d969a3a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
@@ -3,10 +3,10 @@
 
 #include "vf_mulop.h"
 
-DEF_VF_MULOP_CASE_1 (double, +, +, add, VF_MULOP_BODY_X16)
-DEF_VF_MULOP_CASE_1 (double, -, +, sub, VF_MULOP_BODY_X16)
-DEF_VF_MULOP_CASE_1 (double, +, -, nadd, VF_MULOP_BODY_X16)
-DEF_VF_MULOP_CASE_1 (double, -, -, nsub, VF_MULOP_BODY_X16)
+DEF_VF_MULOP_CASE_1 (double, +, +, add, VF_MULOP_BODY_X128)
+DEF_VF_MULOP_CASE_1 (double, -, +, sub, VF_MULOP_BODY_X128)
+DEF_VF_MULOP_CASE_1 (double, +, -, nadd, VF_MULOP_BODY_X128)
+DEF_VF_MULOP_CASE_1 (double, -, -, nsub, VF_MULOP_BODY_X128)
 DEF_VF_MULOP_ACC_CASE_1 (double, +, +, acc, VF_MULOP_ACC_BODY_X128)
 DEF_VF_MULOP_ACC_CASE_1 (double, -, +, sac, VF_MULOP_ACC_BODY_X128)
 DEF_VF_MULOP_ACC_CASE_1 (double, +, -, nacc, VF_MULOP_ACC_BODY_X128)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
index 0bfa2cb754b..9a1ff3aed9f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c
@@ -12,8 +12,8 @@ DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X8)
 DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X8)
-DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8)
-DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4)
+DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X4)
 DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8)
 DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8)
 DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
index 43246bb828c..990f3e418bc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c
@@ -13,7 +13,7 @@ DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X16)
 DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8)
-DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8)
+DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X4)
 DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8)
 DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8)
 DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8)
-- 
2.43.0

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