Thanks Jeff, committed.

Pan

-----Original Message-----
From: Jeff Law <jeffreya...@gmail.com> 
Sent: Sunday, August 10, 2025 11:11 PM
To: Li, Pan2 <pan2...@intel.com>; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp....@gmail.com; Chen, Ken 
<ken.c...@intel.com>; Liu, Hongtao <hongtao....@intel.com>
Subject: Re: [PATCH v1] RISC-V: Refactor the vec_duplicate cost on 
gpr/fpr2vr-cost param



On 8/6/25 8:29 AM, pan2...@intel.com wrote:
> From: Pan Li <pan2...@intel.com>
> 
> The previous cost value for vec_duplicate almost bases on the operators
> like add/minus.  The rtx_cost function try to match them case by case
> and find if it has vec_duplicate, then update the cost values.
> 
> It is Ok when we initially add it but looks confused/redundant as more
> and more operators are involved.  As Robin's suggestion, we only care
> about the sub-rtx has vec_duplicate or not, instead of take care of
> it by operators.
> 
> Thus, this PR would like to refactor that and get rid of the operators
> when compute the vec_duplicate cost.
> 
> The below test suites are passed for this patch series.
> * The rv64gcv fully regression test.
> 
> gcc/ChangeLog:
> 
>       * config/riscv/riscv.cc (get_vector_binary_rtx_cost): Remove.
>       (riscv_rtx_costs): Refactor to serach vec_duplicate on the
>       sub rtx.
> 
> gcc/testsuite/ChangeLog:
> 
>       * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c: Update
>       asm check due to above change.
>       * gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv-nofm.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv64gcv.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-1.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-2.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-3.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fmax_zvfh-4.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-1.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-2.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-3.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh-4.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c: Ditto.
>       * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c: Ditto.
> 
> Signed-off-by: Pan Li <pan2...@intel.com>
Just in case it was missed.  Robin ACK'd and I'll ACK as well.  Thanks 
for revisiting -- I kind of expected that as we built out the varous 
cases that some basic structure would start to become visible and I 
think we're seeing that happen with this patch.

jeff

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