> On 6 Jan 2026, at 18:08, Alice Carlotti <[email protected]> wrote:
>
> On Tue, Jan 06, 2026 at 05:31:47PM +0000, Richard Earnshaw (foss) wrote:
>> On 06/01/2026 17:28, Iain Sandoe wrote:
>>>
>>>
>>>> On 6 Jan 2026, at 17:17, Alice Carlotti <[email protected]> wrote:
>>>>
>>>> On Tue, Jan 06, 2026 at 03:17:40PM +0000, Iain Sandoe wrote:
>>>>> Hi Alice,
>>>>>
>>>>> I don’t see any execution tests for SME - would it be worth having one
>>>>> or two - and the target-supports checks for SME h/w with/without SVE?
>>>>>
>>>>>> On 5 Jan 2026, at 15:42, Alice Carlotti <[email protected]> wrote:
>>>>>>
>>>>>> Some SME tests currently require SVE to be enabled as well. Either mark
>>>>>> this requirement explicitly in the test file (with a pragma), or
>>>>>> eliminate it by modifying the test.
>>>>>>
>>>>>> For some check-function-bodies tests we take both approaches - that is,
>>>>>> we add "+sve" to the existing test, and create a duplicate "+nosve" test
>>>>>> that checks for the use of __arm_get_current_vg in the prologue.
>>>>>
>>>>> As I read this , these changes add +sve unconditionally where is is needed
>>>>> - would it make sense for those tests to be skipped on any target that
>>>>> cannot
>>>>> support SVE?
>>>>
>>>> Do you mean this in the sense of "disable for Darwin because Darwin doesn't
>>>> support SVE (yet)"?
>>>
>>> I mean in the sense of having a target-supports that covers this condition.
>>
>> I think that would only be needed for executable tests. There's no reason
>> why compile-only tests couldn't be run on Darwin or any other target, even
>> those without either SVE or SME.
>>
>> R.
>
> Does GCC/Darwin have a defined ABI for non-streaming SVE registers? If that's
> missing, then it wouldn't be possible to compile non-streaming functions with
> SVE parameters. I can't currently think of any other obstacles to running the
> compile tests.
I will research this in “slow time” and report back at some point; as noted
before
no reason to delay this series - getting the darwin branch into trunk is not a
gcc-16
feasibility.
Iain
>
> Alice
>
>>
>>>
>>> Yes, that would have the effect of disabling the tests for Darwin as things
>>> stand
>>> (I have no idea if they ever plan to include SVE) - but it’s also kind of
>>> future-
>>> proofing against any other target with the same limitation.
>>>
>>>>> (in principle, the compile tests should work OK, but in
>>>>> practice there are differences between the LLVM-based assembler that
>>>>> darwin uses and binutils - which means I have had to disable SVE tests
>>>>> in general.
>>>>
>>>> Do you have any examples of these sorts of issues? I'm aware we've had
>>>> some
>>>> incompatibilities with LLVM in the past, but I don't recall any that would
>>>> be
>>>> relevant here.
>>>
>>> I’ll have to dig some out - but remember that the released toolchains are
>>> currently
>>> around LLVM-17, and therefore do not have fixes present in current LLVM.
>>>
>>> ** These were just observations, not at all important in landing this
>>> series **
>>>
>>> thanks
>>> iain
>>>
>>>
>>>>
>>>> Alice
>>>>
>>>>>
>>>>> thanks
>>>>> Iain
>>>>>
>>>>>>
>>>>>> For vect-dotprod-twoway.c, the issue is that the number of
>>>>>> udot/sdot/whilelo instructions depends on the selected tuning option.
>>>>>> Pass an explicit -mtune option to preserve the expected codegen.
>>>>>>
>>>>>> gcc/testsuite/ChangeLog:
>>>>>>
>>>>>> * g++.target/aarch64/sme/exceptions_2.C: Add +sve pragma.
>>>>>> * g++.target/aarch64/sme/exceptions_2_nosve.C: New test.
>>>>>> * gcc.target/aarch64/sme/acle-asm/ldr_vnum_za_sc.c: Remove
>>>>>> svbool_t parameters.
>>>>>> * gcc.target/aarch64/sme/acle-asm/ldr_za_sc.c: Ditto.
>>>>>> * gcc.target/aarch64/sme/acle-asm/str_vnum_za_sc.c: Ditto.
>>>>>> * gcc.target/aarch64/sme/acle-asm/str_za_sc.c: Ditto.
>>>>>> * gcc.target/aarch64/sme/acle-asm/test_sme_acle.h
>>>>>> (TEST_LOAD_ZA_NOPRED, TEST_STORE_ZA_NOPRED): New macros.
>>>>>> * gcc.target/aarch64/sme/call_sm_switch_1.c: Add +sve pragma.
>>>>>> * gcc.target/aarch64/sme/call_sm_switch_1_nosve.c: New test.
>>>>>> * gcc.target/aarch64/sme/call_sm_switch_3.c: Add +sve pragma.
>>>>>> * gcc.target/aarch64/sme/call_sm_switch_3_nosve.c: New test.
>>>>>> * gcc.target/aarch64/sme/call_sm_switch_5.c: Add +sve pragma.
>>>>>> * gcc.target/aarch64/sme/call_sm_switch_6.c: Add +sve pragma.
>>>>>> * gcc.target/aarch64/sme/call_sm_switch_11.c: Add +sve pragma.
>>>>>> * gcc.target/aarch64/sme/call_sm_switch_11_nosve.c: New test.
>>>>>> * gcc.target/aarch64/sme/inlining_9.c: Add +sve pragma.
>>>>>> * gcc.target/aarch64/sme/inlining_10.c: Add +sve pragma.
>>>>>> * gcc.target/aarch64/sme/inlining_11.c: Add +sve pragma.
>>>>>> * gcc.target/aarch64/sme/pr121028.c: Add +sve to pragma.
>>>>>> * gcc.target/aarch64/sme/vect-dotprod-twoway.c: Add -mtune.
>>>>>> * gcc.target/aarch64/sme2/acle-asm/ldr_zt.c: Use svcntsb instead
>>>>>> of svcntb.
>>>>>> * gcc.target/aarch64/sme2/acle-asm/str_zt.c: Ditto.
>>>>>>
>>>>>>
>>>>>> diff --git a/gcc/testsuite/g++.target/aarch64/sme/exceptions_2.C
>>>>>> b/gcc/testsuite/g++.target/aarch64/sme/exceptions_2.C
>>>>>> index
>>>>>> f791b6ecc5487e949488c338af63aa43f56efdec..b0be27661e634b292afad55cfb3cb56945c51623
>>>>>> 100644
>>>>>> --- a/gcc/testsuite/g++.target/aarch64/sme/exceptions_2.C
>>>>>> +++ b/gcc/testsuite/g++.target/aarch64/sme/exceptions_2.C
>>>>>> @@ -1,6 +1,8 @@
>>>>>> // { dg-options "-O -fno-optimize-sibling-calls" }
>>>>>> // { dg-final { check-function-bodies "**" "" } }
>>>>>>
>>>>>> +#pragma GCC target "+sve"
>>>>>> +
>>>>>> void n_callee();
>>>>>> void s_callee() __arm_streaming;
>>>>>> void sc_callee() __arm_streaming_compatible;
>>>>>> diff --git a/gcc/testsuite/g++.target/aarch64/sme/exceptions_2_nosve.C
>>>>>> b/gcc/testsuite/g++.target/aarch64/sme/exceptions_2_nosve.C
>>>>>> new file mode 100644
>>>>>> index
>>>>>> 0000000000000000000000000000000000000000..4e68ad60f23bb17f71cff9f83ca889918077182b
>>>>>> --- /dev/null
>>>>>> +++ b/gcc/testsuite/g++.target/aarch64/sme/exceptions_2_nosve.C
>>>>>> @@ -0,0 +1,150 @@
>>>>>> +// { dg-options "-O -fno-optimize-sibling-calls" }
>>>>>> +// { dg-final { check-function-bodies "**" "" } }
>>>>>> +
>>>>>> +#pragma GCC target "+nosve"
>>>>>> +
>>>>>> +void n_callee();
>>>>>> +void s_callee() __arm_streaming;
>>>>>> +void sc_callee() __arm_streaming_compatible;
>>>>>> +
>>>>>> +void n_callee_ne() noexcept;
>>>>>> +void s_callee_ne() noexcept __arm_streaming;
>>>>>> +void sc_callee_ne() noexcept __arm_streaming_compatible;
>>>>>> +
>>>>>> +void n_caller1()
>>>>>> +{
>>>>>> + try
>>>>>> + {
>>>>>> + n_callee();
>>>>>> + sc_callee();
>>>>>> + }
>>>>>> + catch (...)
>>>>>> + {
>>>>>> + n_callee_ne();
>>>>>> + sc_callee_ne();
>>>>>> + }
>>>>>> +}
>>>>>> +// { dg-final { scan-assembler
>>>>>> {_Z9n_caller1v:(?:(?!smstart|smstop).)*\tret} } }
>>>>>> +
>>>>>> +/*
>>>>>> +** _Z9n_caller2v:
>>>>>> +** ...
>>>>>> +** bl __arm_get_current_vg
>>>>>> +** str x0, [^\n]+
>>>>>> +** ...
>>>>>> +** bl __cxa_begin_catch
>>>>>> +** smstart sm
>>>>>> +** bl _Z11s_callee_nev
>>>>>> +** smstop sm
>>>>>> +** bl __cxa_end_catch
>>>>>> +** ...
>>>>>> +*/
>>>>>> +void n_caller2()
>>>>>> +{
>>>>>> + try
>>>>>> + {
>>>>>> + n_callee();
>>>>>> + sc_callee();
>>>>>> + }
>>>>>> + catch (...)
>>>>>> + {
>>>>>> + s_callee_ne();
>>>>>> + }
>>>>>> +}
>>>>>> +
>>>>>> +/*
>>>>>> +** _Z9s_caller1v:
>>>>>> +** ...
>>>>>> +** bl __cxa_end_catch
>>>>>> +** smstart sm
>>>>>> +** ...
>>>>>> +*/
>>>>>> +int s_caller1() __arm_streaming
>>>>>> +{
>>>>>> + try
>>>>>> + {
>>>>>> + s_callee();
>>>>>> + return 1;
>>>>>> + }
>>>>>> + catch (...)
>>>>>> + {
>>>>>> + return 2;
>>>>>> + }
>>>>>> +}
>>>>>> +
>>>>>> +/*
>>>>>> +** _Z9s_caller2v:
>>>>>> +** ...
>>>>>> +** bl __cxa_begin_catch
>>>>>> +** smstart sm
>>>>>> +** bl _Z11s_callee_nev
>>>>>> +** smstop sm
>>>>>> +** bl __cxa_end_catch
>>>>>> +** smstart sm
>>>>>> +** ...
>>>>>> +*/
>>>>>> +int s_caller2() __arm_streaming
>>>>>> +{
>>>>>> + try
>>>>>> + {
>>>>>> + n_callee();
>>>>>> + return 1;
>>>>>> + }
>>>>>> + catch (...)
>>>>>> + {
>>>>>> + s_callee_ne();
>>>>>> + return 2;
>>>>>> + }
>>>>>> +}
>>>>>> +
>>>>>> +/*
>>>>>> +** _Z10sc_caller1v:
>>>>>> +** ...
>>>>>> +** bl __arm_get_current_vg
>>>>>> +** str x0, [^\n]+
>>>>>> +** mrs (x[0-9]+), svcr
>>>>>> +** str \2, ([^\n]+)
>>>>>> +** ...
>>>>>> +** bl __cxa_end_catch
>>>>>> +** ldr (x[0-9]+), \3
>>>>>> +** tbz \4, 0, [^\n]+
>>>>>> +** smstart sm
>>>>>> +** ...
>>>>>> +*/
>>>>>> +int sc_caller1() __arm_streaming_compatible
>>>>>> +{
>>>>>> + try
>>>>>> + {
>>>>>> + sc_callee();
>>>>>> + return 1;
>>>>>> + }
>>>>>> + catch (...)
>>>>>> + {
>>>>>> + return 2;
>>>>>> + }
>>>>>> +}
>>>>>> +
>>>>>> +/*
>>>>>> +** _Z10ls_caller1v:
>>>>>> +** ...
>>>>>> +** cntd (x[0-9]+)
>>>>>> +** str \1, [^\n]+
>>>>>> +** ...
>>>>>> +** bl __cxa_begin_catch
>>>>>> +** smstart sm
>>>>>> +** bl _Z12sc_callee_nev
>>>>>> +** smstop sm
>>>>>> +** bl __cxa_end_catch
>>>>>> +** ...
>>>>>> +*/
>>>>>> +__arm_locally_streaming void ls_caller1()
>>>>>> +{
>>>>>> + try
>>>>>> + {
>>>>>> + sc_callee();
>>>>>> + }
>>>>>> + catch (...)
>>>>>> + {
>>>>>> + sc_callee_ne();
>>>>>> + }
>>>>>> +}
>>>>>> diff --git
>>>>>> a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/ldr_vnum_za_sc.c
>>>>>> b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/ldr_vnum_za_sc.c
>>>>>> index
>>>>>> dfc2d139f8197b2e31193a7509575a23570b78c9..09481ccf4dc68b74e113525b4754860f320644a2
>>>>>> 100644
>>>>>> --- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/ldr_vnum_za_sc.c
>>>>>> +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/ldr_vnum_za_sc.c
>>>>>> @@ -9,7 +9,7 @@
>>>>>> ** ldr za\[\1, 0\], \[x1(?:, #0, mul vl)?\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_LOAD_ZA (ldr_vnum_za_0_0,
>>>>>> +TEST_LOAD_ZA_NOPRED (ldr_vnum_za_0_0,
>>>>>> svldr_vnum_za (0, x1, 0),
>>>>>> svldr_vnum_za (0, x1, 0))
>>>>>>
>>>>>> @@ -19,7 +19,7 @@ TEST_LOAD_ZA (ldr_vnum_za_0_0,
>>>>>> ** ldr za\[\1, 1\], \[x1(?:, #1, mul vl)?\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_LOAD_ZA (ldr_vnum_za_0_1,
>>>>>> +TEST_LOAD_ZA_NOPRED (ldr_vnum_za_0_1,
>>>>>> svldr_vnum_za (0, x1, 1),
>>>>>> svldr_vnum_za (0, x1, 1))
>>>>>>
>>>>>> @@ -29,7 +29,7 @@ TEST_LOAD_ZA (ldr_vnum_za_0_1,
>>>>>> ** ldr za\[\1, 0\], \[x1(?:, #0, mul vl)?\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_LOAD_ZA (ldr_vnum_za_1_0,
>>>>>> +TEST_LOAD_ZA_NOPRED (ldr_vnum_za_1_0,
>>>>>> svldr_vnum_za (1, x1, 0),
>>>>>> svldr_vnum_za (1, x1, 0))
>>>>>>
>>>>>> @@ -39,7 +39,7 @@ TEST_LOAD_ZA (ldr_vnum_za_1_0,
>>>>>> ** ldr za\[\1, 2\], \[x1(?:, #2, mul vl)?\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_LOAD_ZA (ldr_vnum_za_1_2,
>>>>>> +TEST_LOAD_ZA_NOPRED (ldr_vnum_za_1_2,
>>>>>> svldr_vnum_za (1, x1, 2),
>>>>>> svldr_vnum_za (1, x1, 2))
>>>>>>
>>>>>> @@ -49,7 +49,7 @@ TEST_LOAD_ZA (ldr_vnum_za_1_2,
>>>>>> ** ldr za\[\1, 0\], \[x1(?:, #0, mul vl)?\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_LOAD_ZA (ldr_vnum_za_w0_0,
>>>>>> +TEST_LOAD_ZA_NOPRED (ldr_vnum_za_w0_0,
>>>>>> svldr_vnum_za (w0, x1, 0),
>>>>>> svldr_vnum_za (w0, x1, 0))
>>>>>>
>>>>>> @@ -59,7 +59,7 @@ TEST_LOAD_ZA (ldr_vnum_za_w0_0,
>>>>>> ** ldr za\[\1, 1\], \[x1, #1, mul vl\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_LOAD_ZA (ldr_vnum_za_w0_1,
>>>>>> +TEST_LOAD_ZA_NOPRED (ldr_vnum_za_w0_1,
>>>>>> svldr_vnum_za (w0, x1, 1),
>>>>>> svldr_vnum_za (w0, x1, 1))
>>>>>>
>>>>>> @@ -69,7 +69,7 @@ TEST_LOAD_ZA (ldr_vnum_za_w0_1,
>>>>>> ** ldr za\[\1, 13\], \[x1, #13, mul vl\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_LOAD_ZA (ldr_vnum_za_w0_13,
>>>>>> +TEST_LOAD_ZA_NOPRED (ldr_vnum_za_w0_13,
>>>>>> svldr_vnum_za (w0, x1, 13),
>>>>>> svldr_vnum_za (w0, x1, 13))
>>>>>>
>>>>>> @@ -79,7 +79,7 @@ TEST_LOAD_ZA (ldr_vnum_za_w0_13,
>>>>>> ** ldr za\[\1, 15\], \[x1, #15, mul vl\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_LOAD_ZA (ldr_vnum_za_w0_15,
>>>>>> +TEST_LOAD_ZA_NOPRED (ldr_vnum_za_w0_15,
>>>>>> svldr_vnum_za (w0, x1, 15),
>>>>>> svldr_vnum_za (w0, x1, 15))
>>>>>>
>>>>>> @@ -96,7 +96,7 @@ TEST_LOAD_ZA (ldr_vnum_za_w0_15,
>>>>>> ** )
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_LOAD_ZA (ldr_vnum_za_w0_16,
>>>>>> +TEST_LOAD_ZA_NOPRED (ldr_vnum_za_w0_16,
>>>>>> svldr_vnum_za (w0, x1, 16),
>>>>>> svldr_vnum_za (w0, x1, 16))
>>>>>>
>>>>>> @@ -113,7 +113,7 @@ TEST_LOAD_ZA (ldr_vnum_za_w0_16,
>>>>>> ** )
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_LOAD_ZA (ldr_vnum_za_w0_m1,
>>>>>> +TEST_LOAD_ZA_NOPRED (ldr_vnum_za_w0_m1,
>>>>>> svldr_vnum_za (w0, x1, -1),
>>>>>> svldr_vnum_za (w0, x1, -1))
>>>>>>
>>>>>> @@ -123,7 +123,7 @@ TEST_LOAD_ZA (ldr_vnum_za_w0_m1,
>>>>>> ** ldr za\[\1, 0\], \[x1(?:, #0, mul vl)?\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_LOAD_ZA (ldr_vnum_za_w0p1_0,
>>>>>> +TEST_LOAD_ZA_NOPRED (ldr_vnum_za_w0p1_0,
>>>>>> svldr_vnum_za (w0 + 1, x1, 0),
>>>>>> svldr_vnum_za (w0 + 1, x1, 0))
>>>>>>
>>>>>> @@ -133,7 +133,7 @@ TEST_LOAD_ZA (ldr_vnum_za_w0p1_0,
>>>>>> ** ldr za\[\1, 1\], \[x1(?:, #1, mul vl)?\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_LOAD_ZA (ldr_vnum_za_w0m1_1,
>>>>>> +TEST_LOAD_ZA_NOPRED (ldr_vnum_za_w0m1_1,
>>>>>> svldr_vnum_za (w0 - 1, x1, 1),
>>>>>> svldr_vnum_za (w0 - 1, x1, 1))
>>>>>>
>>>>>> @@ -143,6 +143,6 @@ TEST_LOAD_ZA (ldr_vnum_za_w0m1_1,
>>>>>> ** ldr za\[\1, 3\], \[x1(?:, #3, mul vl)?\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_LOAD_ZA (ldr_vnum_za_w0p2_3,
>>>>>> +TEST_LOAD_ZA_NOPRED (ldr_vnum_za_w0p2_3,
>>>>>> svldr_vnum_za (w0 + 2, x1, 3),
>>>>>> svldr_vnum_za (w0 + 2, x1, 3))
>>>>>> diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/ldr_za_sc.c
>>>>>> b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/ldr_za_sc.c
>>>>>> index
>>>>>> a27be76719681252e1bfa1867e558955f3c5d0de..a358b016d8abce7d19e549dc6c694c53d6fa5f0c
>>>>>> 100644
>>>>>> --- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/ldr_za_sc.c
>>>>>> +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/ldr_za_sc.c
>>>>>> @@ -9,7 +9,7 @@
>>>>>> ** ldr za\[\1, 0\], \[x1(?:, #0, mul vl)?\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_LOAD_ZA (ldr_za_0,
>>>>>> +TEST_LOAD_ZA_NOPRED (ldr_za_0,
>>>>>> svldr_za (0, x1),
>>>>>> svldr_za (0, x1))
>>>>>>
>>>>>> @@ -19,7 +19,7 @@ TEST_LOAD_ZA (ldr_za_0,
>>>>>> ** ldr za\[\1, 0\], \[x1(?:, #0, mul vl)?\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_LOAD_ZA (ldr_za_1,
>>>>>> +TEST_LOAD_ZA_NOPRED (ldr_za_1,
>>>>>> svldr_za (1, x1),
>>>>>> svldr_za (1, x1))
>>>>>>
>>>>>> @@ -29,7 +29,7 @@ TEST_LOAD_ZA (ldr_za_1,
>>>>>> ** ldr za\[\1, 0\], \[x1(?:, #0, mul vl)?\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_LOAD_ZA (ldr_za_w0,
>>>>>> +TEST_LOAD_ZA_NOPRED (ldr_za_w0,
>>>>>> svldr_za (w0, x1),
>>>>>> svldr_za (w0, x1))
>>>>>>
>>>>>> @@ -39,7 +39,7 @@ TEST_LOAD_ZA (ldr_za_w0,
>>>>>> ** ldr za\[\1, 1\], \[x1, #1, mul vl\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_LOAD_ZA (ldr_za_w0_1_vnum,
>>>>>> +TEST_LOAD_ZA_NOPRED (ldr_za_w0_1_vnum,
>>>>>> svldr_za (w0 + 1, x1 + svcntsb ()),
>>>>>> svldr_za (w0 + 1, x1 + svcntsb ()))
>>>>>>
>>>>>> @@ -49,7 +49,7 @@ TEST_LOAD_ZA (ldr_za_w0_1_vnum,
>>>>>> ** ldr za\[\1, 0\], \[x1(?:, #0, mul vl)?\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_LOAD_ZA (ldr_za_w0p2,
>>>>>> +TEST_LOAD_ZA_NOPRED (ldr_za_w0p2,
>>>>>> svldr_za (w0 + 2, x1),
>>>>>> svldr_za (w0 + 2, x1))
>>>>>>
>>>>>> @@ -66,6 +66,6 @@ TEST_LOAD_ZA (ldr_za_w0p2,
>>>>>> ** )
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_LOAD_ZA (ldr_za_offset,
>>>>>> +TEST_LOAD_ZA_NOPRED (ldr_za_offset,
>>>>>> svldr_za (w0, x1 + 1),
>>>>>> svldr_za (w0, x1 + 1))
>>>>>> diff --git
>>>>>> a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/str_vnum_za_sc.c
>>>>>> b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/str_vnum_za_sc.c
>>>>>> index
>>>>>> 7cd09e67c93596c24f3d9844b326d79dd99f4f82..29dc00c3d5331a7b4b047b13bf14991bc3dea1da
>>>>>> 100644
>>>>>> --- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/str_vnum_za_sc.c
>>>>>> +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/str_vnum_za_sc.c
>>>>>> @@ -9,7 +9,7 @@
>>>>>> ** str za\[\1, 0\], \[x1(?:, #0, mul vl)?\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_STORE_ZA (str_vnum_za_0_0,
>>>>>> +TEST_STORE_ZA_NOPRED (str_vnum_za_0_0,
>>>>>> svstr_vnum_za (0, x1, 0),
>>>>>> svstr_vnum_za (0, x1, 0))
>>>>>>
>>>>>> @@ -19,7 +19,7 @@ TEST_STORE_ZA (str_vnum_za_0_0,
>>>>>> ** str za\[\1, 1\], \[x1(?:, #1, mul vl)?\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_STORE_ZA (str_vnum_za_0_1,
>>>>>> +TEST_STORE_ZA_NOPRED (str_vnum_za_0_1,
>>>>>> svstr_vnum_za (0, x1, 1),
>>>>>> svstr_vnum_za (0, x1, 1))
>>>>>>
>>>>>> @@ -29,7 +29,7 @@ TEST_STORE_ZA (str_vnum_za_0_1,
>>>>>> ** str za\[\1, 0\], \[x1(?:, #0, mul vl)?\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_STORE_ZA (str_vnum_za_1_0,
>>>>>> +TEST_STORE_ZA_NOPRED (str_vnum_za_1_0,
>>>>>> svstr_vnum_za (1, x1, 0),
>>>>>> svstr_vnum_za (1, x1, 0))
>>>>>>
>>>>>> @@ -39,7 +39,7 @@ TEST_STORE_ZA (str_vnum_za_1_0,
>>>>>> ** str za\[\1, 2\], \[x1(?:, #2, mul vl)?\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_STORE_ZA (str_vnum_za_1_2,
>>>>>> +TEST_STORE_ZA_NOPRED (str_vnum_za_1_2,
>>>>>> svstr_vnum_za (1, x1, 2),
>>>>>> svstr_vnum_za (1, x1, 2))
>>>>>>
>>>>>> @@ -49,7 +49,7 @@ TEST_STORE_ZA (str_vnum_za_1_2,
>>>>>> ** str za\[\1, 0\], \[x1(?:, #0, mul vl)?\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_STORE_ZA (str_vnum_za_w0_0,
>>>>>> +TEST_STORE_ZA_NOPRED (str_vnum_za_w0_0,
>>>>>> svstr_vnum_za (w0, x1, 0),
>>>>>> svstr_vnum_za (w0, x1, 0))
>>>>>>
>>>>>> @@ -59,7 +59,7 @@ TEST_STORE_ZA (str_vnum_za_w0_0,
>>>>>> ** str za\[\1, 1\], \[x1, #1, mul vl\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_STORE_ZA (str_vnum_za_w0_1,
>>>>>> +TEST_STORE_ZA_NOPRED (str_vnum_za_w0_1,
>>>>>> svstr_vnum_za (w0, x1, 1),
>>>>>> svstr_vnum_za (w0, x1, 1))
>>>>>>
>>>>>> @@ -69,7 +69,7 @@ TEST_STORE_ZA (str_vnum_za_w0_1,
>>>>>> ** str za\[\1, 13\], \[x1, #13, mul vl\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_STORE_ZA (str_vnum_za_w0_13,
>>>>>> +TEST_STORE_ZA_NOPRED (str_vnum_za_w0_13,
>>>>>> svstr_vnum_za (w0, x1, 13),
>>>>>> svstr_vnum_za (w0, x1, 13))
>>>>>>
>>>>>> @@ -79,7 +79,7 @@ TEST_STORE_ZA (str_vnum_za_w0_13,
>>>>>> ** str za\[\1, 15\], \[x1, #15, mul vl\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_STORE_ZA (str_vnum_za_w0_15,
>>>>>> +TEST_STORE_ZA_NOPRED (str_vnum_za_w0_15,
>>>>>> svstr_vnum_za (w0, x1, 15),
>>>>>> svstr_vnum_za (w0, x1, 15))
>>>>>>
>>>>>> @@ -96,7 +96,7 @@ TEST_STORE_ZA (str_vnum_za_w0_15,
>>>>>> ** )
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_STORE_ZA (str_vnum_za_w0_16,
>>>>>> +TEST_STORE_ZA_NOPRED (str_vnum_za_w0_16,
>>>>>> svstr_vnum_za (w0, x1, 16),
>>>>>> svstr_vnum_za (w0, x1, 16))
>>>>>>
>>>>>> @@ -113,7 +113,7 @@ TEST_STORE_ZA (str_vnum_za_w0_16,
>>>>>> ** )
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_STORE_ZA (str_vnum_za_w0_m1,
>>>>>> +TEST_STORE_ZA_NOPRED (str_vnum_za_w0_m1,
>>>>>> svstr_vnum_za (w0, x1, -1),
>>>>>> svstr_vnum_za (w0, x1, -1))
>>>>>>
>>>>>> @@ -123,7 +123,7 @@ TEST_STORE_ZA (str_vnum_za_w0_m1,
>>>>>> ** str za\[\1, 0\], \[x1(?:, #0, mul vl)?\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_STORE_ZA (str_vnum_za_w0p1_0,
>>>>>> +TEST_STORE_ZA_NOPRED (str_vnum_za_w0p1_0,
>>>>>> svstr_vnum_za (w0 + 1, x1, 0),
>>>>>> svstr_vnum_za (w0 + 1, x1, 0))
>>>>>>
>>>>>> @@ -133,7 +133,7 @@ TEST_STORE_ZA (str_vnum_za_w0p1_0,
>>>>>> ** str za\[\1, 1\], \[x1(?:, #1, mul vl)?\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_STORE_ZA (str_vnum_za_w0m1_1,
>>>>>> +TEST_STORE_ZA_NOPRED (str_vnum_za_w0m1_1,
>>>>>> svstr_vnum_za (w0 - 1, x1, 1),
>>>>>> svstr_vnum_za (w0 - 1, x1, 1))
>>>>>>
>>>>>> @@ -143,6 +143,6 @@ TEST_STORE_ZA (str_vnum_za_w0m1_1,
>>>>>> ** str za\[\1, 3\], \[x1(?:, #3, mul vl)?\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_STORE_ZA (str_vnum_za_w0p2_3,
>>>>>> +TEST_STORE_ZA_NOPRED (str_vnum_za_w0p2_3,
>>>>>> svstr_vnum_za (w0 + 2, x1, 3),
>>>>>> svstr_vnum_za (w0 + 2, x1, 3))
>>>>>> diff --git a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/str_za_sc.c
>>>>>> b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/str_za_sc.c
>>>>>> index
>>>>>> 3406055e70d31955290504f11b4e72280766cd23..a0aa1c7ca7dad74f45cd5c7c7d4a895440186d14
>>>>>> 100644
>>>>>> --- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/str_za_sc.c
>>>>>> +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/str_za_sc.c
>>>>>> @@ -9,7 +9,7 @@
>>>>>> ** str za\[\1, 0\], \[x1(?:, #0, mul vl)?\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_STORE_ZA (str_za_0,
>>>>>> +TEST_STORE_ZA_NOPRED (str_za_0,
>>>>>> svstr_za (0, x1),
>>>>>> svstr_za (0, x1))
>>>>>>
>>>>>> @@ -19,7 +19,7 @@ TEST_STORE_ZA (str_za_0,
>>>>>> ** str za\[\1, 0\], \[x1(?:, #0, mul vl)?\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_STORE_ZA (str_za_1,
>>>>>> +TEST_STORE_ZA_NOPRED (str_za_1,
>>>>>> svstr_za (1, x1),
>>>>>> svstr_za (1, x1))
>>>>>>
>>>>>> @@ -29,7 +29,7 @@ TEST_STORE_ZA (str_za_1,
>>>>>> ** str za\[\1, 0\], \[x1(?:, #0, mul vl)?\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_STORE_ZA (str_za_w0,
>>>>>> +TEST_STORE_ZA_NOPRED (str_za_w0,
>>>>>> svstr_za (w0, x1),
>>>>>> svstr_za (w0, x1))
>>>>>>
>>>>>> @@ -39,7 +39,7 @@ TEST_STORE_ZA (str_za_w0,
>>>>>> ** str za\[\1, 1\], \[x1, #1, mul vl\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_STORE_ZA (str_za_w0_1_vnum,
>>>>>> +TEST_STORE_ZA_NOPRED (str_za_w0_1_vnum,
>>>>>> svstr_za (w0 + 1, x1 + svcntsb ()),
>>>>>> svstr_za (w0 + 1, x1 + svcntsb ()))
>>>>>>
>>>>>> @@ -49,7 +49,7 @@ TEST_STORE_ZA (str_za_w0_1_vnum,
>>>>>> ** str za\[\1, 0\], \[x1(?:, #0, mul vl)?\]
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_STORE_ZA (str_za_w0p2,
>>>>>> +TEST_STORE_ZA_NOPRED (str_za_w0p2,
>>>>>> svstr_za (w0 + 2, x1),
>>>>>> svstr_za (w0 + 2, x1))
>>>>>>
>>>>>> @@ -66,6 +66,6 @@ TEST_STORE_ZA (str_za_w0p2,
>>>>>> ** )
>>>>>> ** ret
>>>>>> */
>>>>>> -TEST_STORE_ZA (str_za_offset,
>>>>>> +TEST_STORE_ZA_NOPRED (str_za_offset,
>>>>>> svstr_za (w0, x1 + 1),
>>>>>> svstr_za (w0, x1 + 1))
>>>>>> diff --git
>>>>>> a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/test_sme_acle.h
>>>>>> b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/test_sme_acle.h
>>>>>> index
>>>>>> 75e3413768e29a0917dc86d25e00f24d78949c81..c81bf074c50173e7f59ce6c9df7074fbb60c37c1
>>>>>> 100644
>>>>>> --- a/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/test_sme_acle.h
>>>>>> +++ b/gcc/testsuite/gcc.target/aarch64/sme/acle-asm/test_sme_acle.h
>>>>>> @@ -29,6 +29,20 @@
>>>>>> INVOKE (CODE1, CODE2); \
>>>>>> }
>>>>>>
>>>>>> +#define TEST_LOAD_ZA_NOPRED(NAME, CODE1, CODE2) \
>>>>>> + PROTO (NAME, void, (int32_t w0, const char *x1, \
>>>>>> + uint64_t x2)) \
>>>>>> + { \
>>>>>> + INVOKE (CODE1, CODE2); \
>>>>>> + }
>>>>>> +
>>>>>> +#define TEST_STORE_ZA_NOPRED(NAME, CODE1, CODE2) \
>>>>>> + PROTO (NAME, void, (int32_t w0, char *x1, \
>>>>>> + uint64_t x2)) \
>>>>>> + { \
>>>>>> + INVOKE (CODE1, CODE2); \
>>>>>> + }
>>>>>> +
>>>>>> #define TEST_READ_ZA(NAME, TYPE, CODE1, CODE2) \
>>>>>> PROTO (NAME, TYPE, (TYPE z0, TYPE z1, svbool_t p0, \
>>>>>> int32_t w0)) \
>>>>>> diff --git a/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_1.c
>>>>>> b/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_1.c
>>>>>> index
>>>>>> 3a63da7439cce7bca22413d63324eb0b6945e4ac..ed4674a6c84af7df6111af01255124f2312bd9d4
>>>>>> 100644
>>>>>> --- a/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_1.c
>>>>>> +++ b/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_1.c
>>>>>> @@ -1,6 +1,8 @@
>>>>>> // { dg-options "-O -fomit-frame-pointer -fno-optimize-sibling-calls
>>>>>> -funwind-tables" }
>>>>>> // { dg-final { check-function-bodies "**" "" "" { target "*-*-*" }
>>>>>> {\t\.inst} } }
>>>>>>
>>>>>> +#pragma GCC target "+sve"
>>>>>> +
>>>>>> void ns_callee ();
>>>>>> void s_callee () [[arm::streaming]];
>>>>>> void sc_callee () [[arm::streaming_compatible]];
>>>>>> diff --git a/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_11.c
>>>>>> b/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_11.c
>>>>>> index
>>>>>> c72d03f33b971e0cdc299ef1795abd60c33b72a6..78ac503f2e2c3fe854ca10e4aa33602b436cd85a
>>>>>> 100644
>>>>>> --- a/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_11.c
>>>>>> +++ b/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_11.c
>>>>>> @@ -1,6 +1,7 @@
>>>>>> // { dg-options "-O -fomit-frame-pointer -fno-optimize-sibling-calls
>>>>>> -funwind-tables -mtrack-speculation" }
>>>>>> // { dg-final { check-function-bodies "**" "" "" { target "*-*-*" }
>>>>>> {\t\.inst} } }
>>>>>>
>>>>>> +#pragma GCC target "+sve"
>>>>>>
>>>>>> void ns_callee ();
>>>>>> void s_callee () [[arm::streaming]];
>>>>>> diff --git
>>>>>> a/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_11_nosve.c
>>>>>> b/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_11_nosve.c
>>>>>> new file mode 100644
>>>>>> index
>>>>>> 0000000000000000000000000000000000000000..8f8b25ad89c0f82a5a1db6b566054d912744a27b
>>>>>> --- /dev/null
>>>>>> +++ b/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_11_nosve.c
>>>>>> @@ -0,0 +1,222 @@
>>>>>> +// { dg-options "-O -fomit-frame-pointer -fno-optimize-sibling-calls
>>>>>> -funwind-tables -mtrack-speculation" }
>>>>>> +// { dg-final { check-function-bodies "**" "" "" { target "*-*-*" }
>>>>>> {\t\.inst} } }
>>>>>> +
>>>>>> +#pragma GCC target "+nosve"
>>>>>> +
>>>>>> +void ns_callee ();
>>>>>> + void s_callee () [[arm::streaming]];
>>>>>> + void sc_callee () [[arm::streaming_compatible]];
>>>>>> +
>>>>>> +void ns_callee_stack (int, int, int, int, int, int, int, int, int);
>>>>>> +
>>>>>> +struct callbacks {
>>>>>> + void (*ns_ptr) ();
>>>>>> + void (*s_ptr) () [[arm::streaming]];
>>>>>> + void (*sc_ptr) () [[arm::streaming_compatible]];
>>>>>> +};
>>>>>> +
>>>>>> +/*
>>>>>> +** sc_caller_sme:
>>>>>> +** cmp sp, #?0
>>>>>> +** csetm x15, ne
>>>>>> +** stp x29, x30, \[sp, #?-96\]!
>>>>>> +** mov x29, sp
>>>>>> +** mov x14, sp
>>>>>> +** and x14, x14, x15
>>>>>> +** mov sp, x14
>>>>>> +** bl __arm_get_current_vg
>>>>>> +** cmp sp, #?0
>>>>>> +** csetm x15, ne
>>>>>> +** str x0, \[sp, #?24\]
>>>>>> +** stp d8, d9, \[sp, #?32\]
>>>>>> +** stp d10, d11, \[sp, #?48\]
>>>>>> +** stp d12, d13, \[sp, #?64\]
>>>>>> +** stp d14, d15, \[sp, #?80\]
>>>>>> +** mrs x16, svcr
>>>>>> +** str x16, \[x29, #?16\]
>>>>>> +** ldr x16, \[x29, #?16\]
>>>>>> +** tst x16, #?1
>>>>>> +** beq [^\n]*
>>>>>> +** csel x15, x15, xzr, ne
>>>>>> +** smstop sm
>>>>>> +** b [^\n]*
>>>>>> +** csel x15, x15, xzr, eq
>>>>>> +** mov x14, sp
>>>>>> +** and x14, x14, x15
>>>>>> +** mov sp, x14
>>>>>> +** bl ns_callee
>>>>>> +** cmp sp, #?0
>>>>>> +** csetm x15, ne
>>>>>> +** ldr x16, \[x29, #?16\]
>>>>>> +** tst x16, #?1
>>>>>> +** beq [^\n]*
>>>>>> +** csel x15, x15, xzr, ne
>>>>>> +** smstart sm
>>>>>> +** b [^\n]*
>>>>>> +** csel x15, x15, xzr, eq
>>>>>> +** ldr x16, \[x29, #?16\]
>>>>>> +** tst x16, #?1
>>>>>> +** bne [^\n]*
>>>>>> +** csel x15, x15, xzr, eq
>>>>>> +** smstart sm
>>>>>> +** b [^\n]*
>>>>>> +** csel x15, x15, xzr, ne
>>>>>> +** mov x14, sp
>>>>>> +** and x14, x14, x15
>>>>>> +** mov sp, x14
>>>>>> +** bl s_callee
>>>>>> +** cmp sp, #?0
>>>>>> +** csetm x15, ne
>>>>>> +** ldr x16, \[x29, #?16\]
>>>>>> +** tst x16, #?1
>>>>>> +** bne [^\n]*
>>>>>> +** csel x15, x15, xzr, eq
>>>>>> +** smstop sm
>>>>>> +** b [^\n]*
>>>>>> +** csel x15, x15, xzr, ne
>>>>>> +** mov x14, sp
>>>>>> +** and x14, x14, x15
>>>>>> +** mov sp, x14
>>>>>> +** bl sc_callee
>>>>>> +** cmp sp, #?0
>>>>>> +** csetm x15, ne
>>>>>> +** ldp d8, d9, \[sp, #?32\]
>>>>>> +** ldp d10, d11, \[sp, #?48\]
>>>>>> +** ldp d12, d13, \[sp, #?64\]
>>>>>> +** ldp d14, d15, \[sp, #?80\]
>>>>>> +** ldp x29, x30, \[sp\], #?96
>>>>>> +** mov x14, sp
>>>>>> +** and x14, x14, x15
>>>>>> +** mov sp, x14
>>>>>> +** ret
>>>>>> +*/
>>>>>> +void
>>>>>> +sc_caller_sme () [[arm::streaming_compatible]]
>>>>>> +{
>>>>>> + ns_callee ();
>>>>>> + s_callee ();
>>>>>> + sc_callee ();
>>>>>> +}
>>>>>> +
>>>>>> +#pragma GCC target "+nosme"
>>>>>> +
>>>>>> +/*
>>>>>> +** sc_caller:
>>>>>> +** cmp sp, #?0
>>>>>> +** csetm x15, ne
>>>>>> +** stp x29, x30, \[sp, #?-96\]!
>>>>>> +** mov x29, sp
>>>>>> +** mov x14, sp
>>>>>> +** and x14, x14, x15
>>>>>> +** mov sp, x14
>>>>>> +** bl __arm_get_current_vg
>>>>>> +** str x0, \[sp, #?24\]
>>>>>> +** stp d8, d9, \[sp, #?32\]
>>>>>> +** stp d10, d11, \[sp, #?48\]
>>>>>> +** stp d12, d13, \[sp, #?64\]
>>>>>> +** stp d14, d15, \[sp, #?80\]
>>>>>> +** bl __arm_sme_state
>>>>>> +** cmp sp, #?0
>>>>>> +** csetm x15, ne
>>>>>> +** str x0, \[x29, #?16\]
>>>>>> +** ...
>>>>>> +** bl sc_callee
>>>>>> +** cmp sp, #?0
>>>>>> +** csetm x15, ne
>>>>>> +** ldp d8, d9, \[sp, #?32\]
>>>>>> +** ldp d10, d11, \[sp, #?48\]
>>>>>> +** ldp d12, d13, \[sp, #?64\]
>>>>>> +** ldp d14, d15, \[sp, #?80\]
>>>>>> +** ldp x29, x30, \[sp\], #?96
>>>>>> +** mov x14, sp
>>>>>> +** and x14, x14, x15
>>>>>> +** mov sp, x14
>>>>>> +** ret
>>>>>> +*/
>>>>>> +void
>>>>>> +sc_caller () [[arm::streaming_compatible]]
>>>>>> +{
>>>>>> + ns_callee ();
>>>>>> + sc_callee ();
>>>>>> +}
>>>>>> +
>>>>>> +/*
>>>>>> +** sc_caller_x0:
>>>>>> +** ...
>>>>>> +** mov x10, x0
>>>>>> +** mov x14, sp
>>>>>> +** and x14, x14, x15
>>>>>> +** mov sp, x14
>>>>>> +** bl __arm_get_current_vg
>>>>>> +** ...
>>>>>> +** bl __arm_sme_state
>>>>>> +** ...
>>>>>> +** str wzr, \[x10\]
>>>>>> +** ...
>>>>>> +*/
>>>>>> +void
>>>>>> +sc_caller_x0 (int *ptr) [[arm::streaming_compatible]]
>>>>>> +{
>>>>>> + *ptr = 0;
>>>>>> + ns_callee ();
>>>>>> + sc_callee ();
>>>>>> +}
>>>>>> +
>>>>>> +/*
>>>>>> +** sc_caller_x1:
>>>>>> +** ...
>>>>>> +** mov x10, x0
>>>>>> +** mov x14, sp
>>>>>> +** and x14, x14, x15
>>>>>> +** mov sp, x14
>>>>>> +** bl __arm_get_current_vg
>>>>>> +** ...
>>>>>> +** mov x11, x1
>>>>>> +** bl __arm_sme_state
>>>>>> +** ...
>>>>>> +** str w11, \[x10\]
>>>>>> +** ...
>>>>>> +*/
>>>>>> +void
>>>>>> +sc_caller_x1 (int *ptr, int a) [[arm::streaming_compatible]]
>>>>>> +{
>>>>>> + *ptr = a;
>>>>>> + ns_callee ();
>>>>>> + sc_callee ();
>>>>>> +}
>>>>>> +
>>>>>> +/*
>>>>>> +** sc_caller_stack:
>>>>>> +** cmp sp, #?0
>>>>>> +** csetm x15, ne
>>>>>> +** sub sp, sp, #112
>>>>>> +** stp x29, x30, \[sp, #?16\]
>>>>>> +** add x29, sp, #?16
>>>>>> +** ...
>>>>>> +** bl __arm_get_current_vg
>>>>>> +** ...
>>>>>> +** stp d8, d9, \[sp, #?48\]
>>>>>> +** ...
>>>>>> +** bl __arm_sme_state
>>>>>> +** cmp sp, #?0
>>>>>> +** csetm x15, ne
>>>>>> +** str x0, \[x29, #?16\]
>>>>>> +** ...
>>>>>> +** bl ns_callee_stack
>>>>>> +** cmp sp, #?0
>>>>>> +** csetm x15, ne
>>>>>> +** ldr x16, \[x29, #?16\]
>>>>>> +** tst x16, #?1
>>>>>> +** beq [^\n]*
>>>>>> +** csel x15, x15, xzr, ne
>>>>>> +** .inst 0xd503437f // smstart sm
>>>>>> +** ...
>>>>>> +*/
>>>>>> +void
>>>>>> +sc_caller_stack () [[arm::streaming_compatible]]
>>>>>> +{
>>>>>> + ns_callee_stack (0, 0, 0, 0, 0, 0, 0, 0, 0);
>>>>>> +}
>>>>>> +
>>>>>> +/* { dg-final { scan-assembler {sc_caller_sme:(?:(?!ret).)*\.cfi_offset
>>>>>> 46, -72\n} } } */
>>>>>> +/* { dg-final { scan-assembler {sc_caller:(?:(?!ret).)*\.cfi_offset 46,
>>>>>> -72\n} } } */
>>>>>> diff --git
>>>>>> a/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_1_nosve.c
>>>>>> b/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_1_nosve.c
>>>>>> new file mode 100644
>>>>>> index
>>>>>> 0000000000000000000000000000000000000000..970fa4a3cc147265a47a228030d03d458da368f5
>>>>>> --- /dev/null
>>>>>> +++ b/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_1_nosve.c
>>>>>> @@ -0,0 +1,240 @@
>>>>>> +// { dg-options "-O -fomit-frame-pointer -fno-optimize-sibling-calls
>>>>>> -funwind-tables" }
>>>>>> +// { dg-final { check-function-bodies "**" "" "" { target "*-*-*" }
>>>>>> {\t\.inst} } }
>>>>>> +
>>>>>> +#pragma GCC target "+nosve"
>>>>>> +
>>>>>> +void ns_callee ();
>>>>>> + void s_callee () [[arm::streaming]];
>>>>>> + void sc_callee () [[arm::streaming_compatible]];
>>>>>> +
>>>>>> +void ns_callee_stack (int, int, int, int, int, int, int, int, int);
>>>>>> +
>>>>>> +struct callbacks {
>>>>>> + void (*ns_ptr) ();
>>>>>> + void (*s_ptr) () [[arm::streaming]];
>>>>>> + void (*sc_ptr) () [[arm::streaming_compatible]];
>>>>>> +};
>>>>>> +
>>>>>> +/*
>>>>>> +** n_caller: { target lp64 }
>>>>>> +** stp x30, (x19|x2[0-8]), \[sp, #?-96\]!
>>>>>> +** mov (x9|x1[0-5]), x0
>>>>>> +** bl __arm_get_current_vg
>>>>>> +** str x0, \[sp, #?16\]
>>>>>> +** stp d8, d9, \[sp, #?32\]
>>>>>> +** stp d10, d11, \[sp, #?48\]
>>>>>> +** stp d12, d13, \[sp, #?64\]
>>>>>> +** stp d14, d15, \[sp, #?80\]
>>>>>> +** mov \1, \2
>>>>>> +** bl ns_callee
>>>>>> +** smstart sm
>>>>>> +** bl s_callee
>>>>>> +** smstop sm
>>>>>> +** bl sc_callee
>>>>>> +** ldr (x[0-9]+), \[\1\]
>>>>>> +** blr \3
>>>>>> +** ldr (x[0-9]+), \[\1, #?8\]
>>>>>> +** smstart sm
>>>>>> +** blr \4
>>>>>> +** smstop sm
>>>>>> +** ldr (x[0-9]+), \[\1, #?16\]
>>>>>> +** blr \5
>>>>>> +** ldp d8, d9, \[sp, #?32\]
>>>>>> +** ldp d10, d11, \[sp, #?48\]
>>>>>> +** ldp d12, d13, \[sp, #?64\]
>>>>>> +** ldp d14, d15, \[sp, #?80\]
>>>>>> +** ldp x30, \1, \[sp\], #?96
>>>>>> +** ret
>>>>>> +*/
>>>>>> +void
>>>>>> +n_caller (struct callbacks *c)
>>>>>> +{
>>>>>> + ns_callee ();
>>>>>> + s_callee ();
>>>>>> + sc_callee ();
>>>>>> +
>>>>>> + c->ns_ptr ();
>>>>>> + c->s_ptr ();
>>>>>> + c->sc_ptr ();
>>>>>> +}
>>>>>> +
>>>>>> +/*
>>>>>> +** s_caller: { target lp64 }
>>>>>> +** stp x30, (x19|x2[0-8]), \[sp, #?-96\]!
>>>>>> +** cntd x16
>>>>>> +** str x16, \[sp, #?16\]
>>>>>> +** stp d8, d9, \[sp, #?32\]
>>>>>> +** stp d10, d11, \[sp, #?48\]
>>>>>> +** stp d12, d13, \[sp, #?64\]
>>>>>> +** stp d14, d15, \[sp, #?80\]
>>>>>> +** mov \1, x0
>>>>>> +** smstop sm
>>>>>> +** bl ns_callee
>>>>>> +** smstart sm
>>>>>> +** bl s_callee
>>>>>> +** bl sc_callee
>>>>>> +** ldr (x[0-9]+), \[\1\]
>>>>>> +** smstop sm
>>>>>> +** blr \2
>>>>>> +** smstart sm
>>>>>> +** ldr (x[0-9]+), \[\1, #?8\]
>>>>>> +** blr \3
>>>>>> +** ldr (x[0-9]+), \[\1, #?16\]
>>>>>> +** blr \4
>>>>>> +** ldp d8, d9, \[sp, #?32\]
>>>>>> +** ldp d10, d11, \[sp, #?48\]
>>>>>> +** ldp d12, d13, \[sp, #?64\]
>>>>>> +** ldp d14, d15, \[sp, #?80\]
>>>>>> +** ldp x30, \1, \[sp\], #?96
>>>>>> +** ret
>>>>>> +*/
>>>>>> +void
>>>>>> +s_caller (struct callbacks *c) [[arm::streaming]]
>>>>>> +{
>>>>>> + ns_callee ();
>>>>>> + s_callee ();
>>>>>> + sc_callee ();
>>>>>> +
>>>>>> + c->ns_ptr ();
>>>>>> + c->s_ptr ();
>>>>>> + c->sc_ptr ();
>>>>>> +}
>>>>>> +
>>>>>> +/*
>>>>>> +** sc_caller_sme:
>>>>>> +** stp x29, x30, \[sp, #?-96\]!
>>>>>> +** mov x29, sp
>>>>>> +** bl __arm_get_current_vg
>>>>>> +** str x0, \[sp, #?24\]
>>>>>> +** stp d8, d9, \[sp, #?32\]
>>>>>> +** stp d10, d11, \[sp, #?48\]
>>>>>> +** stp d12, d13, \[sp, #?64\]
>>>>>> +** stp d14, d15, \[sp, #?80\]
>>>>>> +** mrs x16, svcr
>>>>>> +** str x16, \[x29, #?16\]
>>>>>> +** ldr x16, \[x29, #?16\]
>>>>>> +** tbz x16, 0, .*
>>>>>> +** smstop sm
>>>>>> +** bl ns_callee
>>>>>> +** ldr x16, \[x29, #?16\]
>>>>>> +** tbz x16, 0, .*
>>>>>> +** smstart sm
>>>>>> +** ldr x16, \[x29, #?16\]
>>>>>> +** tbnz x16, 0, .*
>>>>>> +** smstart sm
>>>>>> +** bl s_callee
>>>>>> +** ldr x16, \[x29, #?16\]
>>>>>> +** tbnz x16, 0, .*
>>>>>> +** smstop sm
>>>>>> +** bl sc_callee
>>>>>> +** ldp d8, d9, \[sp, #?32\]
>>>>>> +** ldp d10, d11, \[sp, #?48\]
>>>>>> +** ldp d12, d13, \[sp, #?64\]
>>>>>> +** ldp d14, d15, \[sp, #?80\]
>>>>>> +** ldp x29, x30, \[sp\], #?96
>>>>>> +** ret
>>>>>> +*/
>>>>>> +void
>>>>>> +sc_caller_sme () [[arm::streaming_compatible]]
>>>>>> +{
>>>>>> + ns_callee ();
>>>>>> + s_callee ();
>>>>>> + sc_callee ();
>>>>>> +}
>>>>>> +
>>>>>> +#pragma GCC target "+nosme"
>>>>>> +
>>>>>> +/*
>>>>>> +** sc_caller:
>>>>>> +** stp x29, x30, \[sp, #?-96\]!
>>>>>> +** mov x29, sp
>>>>>> +** bl __arm_get_current_vg
>>>>>> +** str x0, \[sp, #?24\]
>>>>>> +** stp d8, d9, \[sp, #?32\]
>>>>>> +** stp d10, d11, \[sp, #?48\]
>>>>>> +** stp d12, d13, \[sp, #?64\]
>>>>>> +** stp d14, d15, \[sp, #?80\]
>>>>>> +** bl __arm_sme_state
>>>>>> +** str x0, \[x29, #?16\]
>>>>>> +** ...
>>>>>> +** bl sc_callee
>>>>>> +** ldp d8, d9, \[sp, #?32\]
>>>>>> +** ldp d10, d11, \[sp, #?48\]
>>>>>> +** ldp d12, d13, \[sp, #?64\]
>>>>>> +** ldp d14, d15, \[sp, #?80\]
>>>>>> +** ldp x29, x30, \[sp\], #?96
>>>>>> +** ret
>>>>>> +*/
>>>>>> +void
>>>>>> +sc_caller () [[arm::streaming_compatible]]
>>>>>> +{
>>>>>> + ns_callee ();
>>>>>> + sc_callee ();
>>>>>> +}
>>>>>> +
>>>>>> +/*
>>>>>> +** sc_caller_x0:
>>>>>> +** ...
>>>>>> +** mov x10, x0
>>>>>> +** bl __arm_get_current_vg
>>>>>> +** ...
>>>>>> +** bl __arm_sme_state
>>>>>> +** ...
>>>>>> +** str wzr, \[x10\]
>>>>>> +** ...
>>>>>> +*/
>>>>>> +void
>>>>>> +sc_caller_x0 (int *ptr) [[arm::streaming_compatible]]
>>>>>> +{
>>>>>> + *ptr = 0;
>>>>>> + ns_callee ();
>>>>>> + sc_callee ();
>>>>>> +}
>>>>>> +
>>>>>> +/*
>>>>>> +** sc_caller_x1:
>>>>>> +** ...
>>>>>> +** mov x10, x0
>>>>>> +** bl __arm_get_current_vg
>>>>>> +** ...
>>>>>> +** mov x11, x1
>>>>>> +** bl __arm_sme_state
>>>>>> +** ...
>>>>>> +** str w11, \[x10\]
>>>>>> +** ...
>>>>>> +*/
>>>>>> +void
>>>>>> +sc_caller_x1 (int *ptr, int a) [[arm::streaming_compatible]]
>>>>>> +{
>>>>>> + *ptr = a;
>>>>>> + ns_callee ();
>>>>>> + sc_callee ();
>>>>>> +}
>>>>>> +
>>>>>> +/*
>>>>>> +** sc_caller_stack:
>>>>>> +** sub sp, sp, #112
>>>>>> +** stp x29, x30, \[sp, #?16\]
>>>>>> +** add x29, sp, #?16
>>>>>> +** ...
>>>>>> +** stp d8, d9, \[sp, #?48\]
>>>>>> +** ...
>>>>>> +** bl __arm_sme_state
>>>>>> +** str x0, \[x29, #?16\]
>>>>>> +** ...
>>>>>> +** bl ns_callee_stack
>>>>>> +** ldr x16, \[x29, #?16\]
>>>>>> +** tbz x16, 0, .*
>>>>>> +** .inst 0xd503437f // smstart sm
>>>>>> +** ...
>>>>>> +*/
>>>>>> +void
>>>>>> +sc_caller_stack () [[arm::streaming_compatible]]
>>>>>> +{
>>>>>> + ns_callee_stack (0, 0, 0, 0, 0, 0, 0, 0, 0);
>>>>>> +}
>>>>>> +
>>>>>> +/* { dg-final { scan-assembler {n_caller:(?:(?!ret).)*\.cfi_offset 46,
>>>>>> -80\n} } } */
>>>>>> +/* { dg-final { scan-assembler {s_caller:(?:(?!ret).)*\.cfi_offset 46,
>>>>>> -80\n} } } */
>>>>>> +/* { dg-final { scan-assembler {sc_caller_sme:(?:(?!ret).)*\.cfi_offset
>>>>>> 46, -72\n} } } */
>>>>>> +/* { dg-final { scan-assembler {sc_caller:(?:(?!ret).)*\.cfi_offset 46,
>>>>>> -72\n} } } */
>>>>>> diff --git a/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_3.c
>>>>>> b/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_3.c
>>>>>> index
>>>>>> 4250fe7984cd363dbfb3b24300133a900852ebec..cdfd31340103f776299d17c861320691623255ce
>>>>>> 100644
>>>>>> --- a/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_3.c
>>>>>> +++ b/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_3.c
>>>>>> @@ -1,6 +1,8 @@
>>>>>> // { dg-options "-O -fomit-frame-pointer -fno-optimize-sibling-calls
>>>>>> -funwind-tables" }
>>>>>> // { dg-final { check-function-bodies "**" "" } }
>>>>>>
>>>>>> +#pragma GCC target "+sve"
>>>>>> +
>>>>>> __attribute__((aarch64_vector_pcs)) void ns_callee ();
>>>>>> __attribute__((aarch64_vector_pcs)) void s_callee () [[arm::streaming]];
>>>>>> __attribute__((aarch64_vector_pcs)) void sc_callee ()
>>>>>> [[arm::streaming_compatible]];
>>>>>> diff --git
>>>>>> a/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_3_nosve.c
>>>>>> b/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_3_nosve.c
>>>>>> new file mode 100644
>>>>>> index
>>>>>> 0000000000000000000000000000000000000000..9a1b4af20c977e1753c7fe0c3603272df07f50a3
>>>>>> --- /dev/null
>>>>>> +++ b/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_3_nosve.c
>>>>>> @@ -0,0 +1,169 @@
>>>>>> +// { dg-options "-O -fomit-frame-pointer -fno-optimize-sibling-calls
>>>>>> -funwind-tables" }
>>>>>> +// { dg-final { check-function-bodies "**" "" } }
>>>>>> +
>>>>>> +#pragma GCC target "+nosve"
>>>>>> +
>>>>>> +__attribute__((aarch64_vector_pcs)) void ns_callee ();
>>>>>> +__attribute__((aarch64_vector_pcs)) void s_callee () [[arm::streaming]];
>>>>>> +__attribute__((aarch64_vector_pcs)) void sc_callee ()
>>>>>> [[arm::streaming_compatible]];
>>>>>> +
>>>>>> +struct callbacks {
>>>>>> + __attribute__((aarch64_vector_pcs)) void (*ns_ptr) ();
>>>>>> + __attribute__((aarch64_vector_pcs)) void (*s_ptr) ()
>>>>>> [[arm::streaming]];
>>>>>> + __attribute__((aarch64_vector_pcs)) void (*sc_ptr) ()
>>>>>> [[arm::streaming_compatible]];
>>>>>> +};
>>>>>> +
>>>>>> +/*
>>>>>> +** n_caller: { target lp64 }
>>>>>> +** stp x30, (x19|x2[0-8]), \[sp, #?-288\]!
>>>>>> +** mov (x9|x1[0-5]), x0
>>>>>> +** bl __arm_get_current_vg
>>>>>> +** str x0, \[sp, #?16\]
>>>>>> +** stp q8, q9, \[sp, #?32\]
>>>>>> +** stp q10, q11, \[sp, #?64\]
>>>>>> +** stp q12, q13, \[sp, #?96\]
>>>>>> +** stp q14, q15, \[sp, #?128\]
>>>>>> +** stp q16, q17, \[sp, #?160\]
>>>>>> +** stp q18, q19, \[sp, #?192\]
>>>>>> +** stp q20, q21, \[sp, #?224\]
>>>>>> +** stp q22, q23, \[sp, #?256\]
>>>>>> +** mov \1, \2
>>>>>> +** bl ns_callee
>>>>>> +** smstart sm
>>>>>> +** bl s_callee
>>>>>> +** smstop sm
>>>>>> +** bl sc_callee
>>>>>> +** ldr (x[0-9]+), \[\1\]
>>>>>> +** blr \3
>>>>>> +** ldr (x[0-9]+), \[\1, #?8\]
>>>>>> +** smstart sm
>>>>>> +** blr \4
>>>>>> +** smstop sm
>>>>>> +** ldr (x[0-9]+), \[\1, #?16\]
>>>>>> +** blr \5
>>>>>> +** ldp q8, q9, \[sp, #?32\]
>>>>>> +** ldp q10, q11, \[sp, #?64\]
>>>>>> +** ldp q12, q13, \[sp, #?96\]
>>>>>> +** ldp q14, q15, \[sp, #?128\]
>>>>>> +** ldp q16, q17, \[sp, #?160\]
>>>>>> +** ldp q18, q19, \[sp, #?192\]
>>>>>> +** ldp q20, q21, \[sp, #?224\]
>>>>>> +** ldp q22, q23, \[sp, #?256\]
>>>>>> +** ldp x30, \1, \[sp\], #?288
>>>>>> +** ret
>>>>>> +*/
>>>>>> +void __attribute__((aarch64_vector_pcs))
>>>>>> +n_caller (struct callbacks *c)
>>>>>> +{
>>>>>> + ns_callee ();
>>>>>> + s_callee ();
>>>>>> + sc_callee ();
>>>>>> +
>>>>>> + c->ns_ptr ();
>>>>>> + c->s_ptr ();
>>>>>> + c->sc_ptr ();
>>>>>> +}
>>>>>> +
>>>>>> +/*
>>>>>> +** s_caller: { target lp64 }
>>>>>> +** stp x30, (x19|x2[0-8]), \[sp, #?-288\]!
>>>>>> +** cntd x16
>>>>>> +** str x16, \[sp, #?16\]
>>>>>> +** stp q8, q9, \[sp, #?32\]
>>>>>> +** stp q10, q11, \[sp, #?64\]
>>>>>> +** stp q12, q13, \[sp, #?96\]
>>>>>> +** stp q14, q15, \[sp, #?128\]
>>>>>> +** stp q16, q17, \[sp, #?160\]
>>>>>> +** stp q18, q19, \[sp, #?192\]
>>>>>> +** stp q20, q21, \[sp, #?224\]
>>>>>> +** stp q22, q23, \[sp, #?256\]
>>>>>> +** mov \1, x0
>>>>>> +** smstop sm
>>>>>> +** bl ns_callee
>>>>>> +** smstart sm
>>>>>> +** bl s_callee
>>>>>> +** bl sc_callee
>>>>>> +** ldr (x[0-9]+), \[\1\]
>>>>>> +** smstop sm
>>>>>> +** blr \2
>>>>>> +** smstart sm
>>>>>> +** ldr (x[0-9]+), \[\1, #?8\]
>>>>>> +** blr \3
>>>>>> +** ldr (x[0-9]+), \[\1, #?16\]
>>>>>> +** blr \4
>>>>>> +** ldp q8, q9, \[sp, #?32\]
>>>>>> +** ldp q10, q11, \[sp, #?64\]
>>>>>> +** ldp q12, q13, \[sp, #?96\]
>>>>>> +** ldp q14, q15, \[sp, #?128\]
>>>>>> +** ldp q16, q17, \[sp, #?160\]
>>>>>> +** ldp q18, q19, \[sp, #?192\]
>>>>>> +** ldp q20, q21, \[sp, #?224\]
>>>>>> +** ldp q22, q23, \[sp, #?256\]
>>>>>> +** ldp x30, \1, \[sp\], #?288
>>>>>> +** ret
>>>>>> +*/
>>>>>> +void __attribute__((aarch64_vector_pcs))
>>>>>> +s_caller (struct callbacks *c) [[arm::streaming]]
>>>>>> +{
>>>>>> + ns_callee ();
>>>>>> + s_callee ();
>>>>>> + sc_callee ();
>>>>>> +
>>>>>> + c->ns_ptr ();
>>>>>> + c->s_ptr ();
>>>>>> + c->sc_ptr ();
>>>>>> +}
>>>>>> +
>>>>>> +/*
>>>>>> +** sc_caller:
>>>>>> +** stp x29, x30, \[sp, #?-288\]!
>>>>>> +** mov x29, sp
>>>>>> +** bl __arm_get_current_vg
>>>>>> +** str x0, \[sp, #?24\]
>>>>>> +** stp q8, q9, \[sp, #?32\]
>>>>>> +** stp q10, q11, \[sp, #?64\]
>>>>>> +** stp q12, q13, \[sp, #?96\]
>>>>>> +** stp q14, q15, \[sp, #?128\]
>>>>>> +** stp q16, q17, \[sp, #?160\]
>>>>>> +** stp q18, q19, \[sp, #?192\]
>>>>>> +** stp q20, q21, \[sp, #?224\]
>>>>>> +** stp q22, q23, \[sp, #?256\]
>>>>>> +** mrs x16, svcr
>>>>>> +** str x16, \[x29, #?16\]
>>>>>> +** ldr x16, \[x29, #?16\]
>>>>>> +** tbz x16, 0, .*
>>>>>> +** smstop sm
>>>>>> +** bl ns_callee
>>>>>> +** ldr x16, \[x29, #?16\]
>>>>>> +** tbz x16, 0, .*
>>>>>> +** smstart sm
>>>>>> +** ldr x16, \[x29, #?16\]
>>>>>> +** tbnz x16, 0, .*
>>>>>> +** smstart sm
>>>>>> +** bl s_callee
>>>>>> +** ldr x16, \[x29, #?16\]
>>>>>> +** tbnz x16, 0, .*
>>>>>> +** smstop sm
>>>>>> +** bl sc_callee
>>>>>> +** ldp q8, q9, \[sp, #?32\]
>>>>>> +** ldp q10, q11, \[sp, #?64\]
>>>>>> +** ldp q12, q13, \[sp, #?96\]
>>>>>> +** ldp q14, q15, \[sp, #?128\]
>>>>>> +** ldp q16, q17, \[sp, #?160\]
>>>>>> +** ldp q18, q19, \[sp, #?192\]
>>>>>> +** ldp q20, q21, \[sp, #?224\]
>>>>>> +** ldp q22, q23, \[sp, #?256\]
>>>>>> +** ldp x29, x30, \[sp\], #?288
>>>>>> +** ret
>>>>>> +*/
>>>>>> +void __attribute__((aarch64_vector_pcs))
>>>>>> +sc_caller () [[arm::streaming_compatible]]
>>>>>> +{
>>>>>> + ns_callee ();
>>>>>> + s_callee ();
>>>>>> + sc_callee ();
>>>>>> +}
>>>>>> +
>>>>>> +/* { dg-final { scan-assembler {n_caller:(?:(?!ret).)*\.cfi_offset 46,
>>>>>> -272\n} } } */
>>>>>> +/* { dg-final { scan-assembler {s_caller:(?:(?!ret).)*\.cfi_offset 46,
>>>>>> -272\n} } } */
>>>>>> +/* { dg-final { scan-assembler {sc_caller:(?:(?!ret).)*\.cfi_offset 46,
>>>>>> -264\n} } } */
>>>>>> diff --git a/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_5.c
>>>>>> b/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_5.c
>>>>>> index
>>>>>> d31b6b91f1f02bb30a9d9925460f9590b103d8e0..86ebfcdcadaf6be6316a3fbedd0de1efe2271900
>>>>>> 100644
>>>>>> --- a/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_5.c
>>>>>> +++ b/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_5.c
>>>>>> @@ -3,6 +3,8 @@
>>>>>>
>>>>>> #include <arm_sve.h>
>>>>>>
>>>>>> +#pragma GCC target "+sve"
>>>>>> +
>>>>>> svbool_t ns_callee ();
>>>>>> svbool_t s_callee () [[arm::streaming]];
>>>>>> svbool_t sc_callee () [[arm::streaming_compatible]];
>>>>>> diff --git a/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_6.c
>>>>>> b/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_6.c
>>>>>> index
>>>>>> 0f6bc4f6c9a5037936fcfb4f58540954a99d3fb0..165a4407d6f1edc958f063cb0b27e09ee041f313
>>>>>> 100644
>>>>>> --- a/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_6.c
>>>>>> +++ b/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_6.c
>>>>>> @@ -2,6 +2,8 @@
>>>>>>
>>>>>> #include <arm_sve.h>
>>>>>>
>>>>>> +#pragma GCC target "+sve"
>>>>>> +
>>>>>> svbool_t ns_callee ();
>>>>>> svbool_t s_callee () [[arm::streaming]];
>>>>>> svbool_t sc_callee () [[arm::streaming_compatible]];
>>>>>> diff --git a/gcc/testsuite/gcc.target/aarch64/sme/inlining_10.c
>>>>>> b/gcc/testsuite/gcc.target/aarch64/sme/inlining_10.c
>>>>>> index
>>>>>> adfd45a872fd5544c99daf7eb9900cddec0512e4..78e737e2f40bc9296b59f44666b9e927c1cd85b3
>>>>>> 100644
>>>>>> --- a/gcc/testsuite/gcc.target/aarch64/sme/inlining_10.c
>>>>>> +++ b/gcc/testsuite/gcc.target/aarch64/sme/inlining_10.c
>>>>>> @@ -3,6 +3,8 @@
>>>>>> #include <arm_neon.h>
>>>>>> #include <arm_sme.h>
>>>>>>
>>>>>> +#pragma GCC target "+sve"
>>>>>> +
>>>>>> uint8x16_t *neon;
>>>>>> svint64_t *sve;
>>>>>> int64_t *ptr;
>>>>>> diff --git a/gcc/testsuite/gcc.target/aarch64/sme/inlining_11.c
>>>>>> b/gcc/testsuite/gcc.target/aarch64/sme/inlining_11.c
>>>>>> index
>>>>>> d05a92c1c24f3efa3c290dd095f25066d33fcc40..0cd3487973e3212516a09ebf794cae4b019a27ef
>>>>>> 100644
>>>>>> --- a/gcc/testsuite/gcc.target/aarch64/sme/inlining_11.c
>>>>>> +++ b/gcc/testsuite/gcc.target/aarch64/sme/inlining_11.c
>>>>>> @@ -3,6 +3,8 @@
>>>>>> #include <arm_neon.h>
>>>>>> #include <arm_sme.h>
>>>>>>
>>>>>> +#pragma GCC target "+sve"
>>>>>> +
>>>>>> uint8x16_t *neon;
>>>>>> svint64_t *sve;
>>>>>> int64_t *ptr;
>>>>>> diff --git a/gcc/testsuite/gcc.target/aarch64/sme/inlining_9.c
>>>>>> b/gcc/testsuite/gcc.target/aarch64/sme/inlining_9.c
>>>>>> index
>>>>>> 91520e3787b1df93cc3482e64e036a271afd4296..dfbfbcae8f362a098d7ee492b39cc68ff3b6109f
>>>>>> 100644
>>>>>> --- a/gcc/testsuite/gcc.target/aarch64/sme/inlining_9.c
>>>>>> +++ b/gcc/testsuite/gcc.target/aarch64/sme/inlining_9.c
>>>>>> @@ -3,6 +3,8 @@
>>>>>> #include <arm_neon.h>
>>>>>> #include <arm_sme.h>
>>>>>>
>>>>>> +#pragma GCC target "+sve"
>>>>>> +
>>>>>> uint8x16_t *neon;
>>>>>> svint64_t *sve;
>>>>>> int64_t *ptr;
>>>>>> diff --git a/gcc/testsuite/gcc.target/aarch64/sme/pr121028.c
>>>>>> b/gcc/testsuite/gcc.target/aarch64/sme/pr121028.c
>>>>>> index
>>>>>> a6aa11900f2ecdeb09f55646939737b23af649bb..b06e011c033da68f3f117c209458e472b68a6769
>>>>>> 100644
>>>>>> --- a/gcc/testsuite/gcc.target/aarch64/sme/pr121028.c
>>>>>> +++ b/gcc/testsuite/gcc.target/aarch64/sme/pr121028.c
>>>>>> @@ -24,7 +24,9 @@ void sc_caller_sme() __arm_streaming_compatible
>>>>>> ns_callee ();
>>>>>> }
>>>>>>
>>>>>> -#pragma GCC target "+nosme"
>>>>>> +/* Add +sve to prevent passing +fcma to the assembler, since +fcma was
>>>>>> + added to assemblers later than SME support. */
>>>>>> +#pragma GCC target "+sve+nosme"
>>>>>>
>>>>>> /*
>>>>>> ** sc_caller_nosme:
>>>>>> diff --git a/gcc/testsuite/gcc.target/aarch64/sme/vect-dotprod-twoway.c
>>>>>> b/gcc/testsuite/gcc.target/aarch64/sme/vect-dotprod-twoway.c
>>>>>> index
>>>>>> 77a019a2f388ecc2fe472a770763b1755802c2a1..c8b68c797272451abfaf70b78b47f5ef773beb9e
>>>>>> 100644
>>>>>> --- a/gcc/testsuite/gcc.target/aarch64/sme/vect-dotprod-twoway.c
>>>>>> +++ b/gcc/testsuite/gcc.target/aarch64/sme/vect-dotprod-twoway.c
>>>>>> @@ -1,4 +1,4 @@
>>>>>> -/* { dg-additional-options "-O2 -ftree-vectorize" } */
>>>>>> +/* { dg-additional-options "-O2 -ftree-vectorize
>>>>>> -mtune=generic-armv9-a" } */
>>>>>>
>>>>>> #include <stdint.h>
>>>>>> #pragma GCC target "+sme2"
>>>>>> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/ldr_zt.c
>>>>>> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/ldr_zt.c
>>>>>> index
>>>>>> a614fbc9537cb8692bc1e266c5504872bdcc4a58..1baf719fb0a449ce89bca3f9d7a9043cc4297341
>>>>>> 100644
>>>>>> --- a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/ldr_zt.c
>>>>>> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/ldr_zt.c
>>>>>> @@ -29,8 +29,8 @@ PROTO (ldr_zt0_x0p64, void, (char *x0)) { svldr_zt (0,
>>>>>> x0 + 64); }
>>>>>>
>>>>>> /*
>>>>>> ** ldr_zt0_x0_vl1:
>>>>>> -** incb x0
>>>>>> +** addsvl x0, x0, #?1
>>>>>> ** ldr zt0, \[x0\]
>>>>>> ** ret
>>>>>> */
>>>>>> -PROTO (ldr_zt0_x0_vl1, void, (char *x0)) { svldr_zt (0, x0 + svcntb());
>>>>>> }
>>>>>> +PROTO (ldr_zt0_x0_vl1, void, (char *x0)) { svldr_zt (0, x0 +
>>>>>> svcntsb()); }
>>>>>> diff --git a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/str_zt.c
>>>>>> b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/str_zt.c
>>>>>> index
>>>>>> c8ecacb10a01db4d98be08f28741f8ec06f17f5e..9e146ed1fc8db18b5d248b1c251e0d28d18b3bd1
>>>>>> 100644
>>>>>> --- a/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/str_zt.c
>>>>>> +++ b/gcc/testsuite/gcc.target/aarch64/sme2/acle-asm/str_zt.c
>>>>>> @@ -29,8 +29,8 @@ PROTO (str_zt0_x0p64, void, (char *x0)) { svstr_zt (0,
>>>>>> x0 + 64); }
>>>>>>
>>>>>> /*
>>>>>> ** str_zt0_x0_vl1:
>>>>>> -** incb x0
>>>>>> +** addsvl x0, x0, #?1
>>>>>> ** str zt0, \[x0\]
>>>>>> ** ret
>>>>>> */
>>>>>> -PROTO (str_zt0_x0_vl1, void, (char *x0)) { svstr_zt (0, x0 + svcntb());
>>>>>> }
>>>>>> +PROTO (str_zt0_x0_vl1, void, (char *x0)) { svstr_zt (0, x0 +
>>>>>> svcntsb()); }
