Re：Re：[PATCH] RISC-V: Add tuning info and vector cost model for xt-c9501fdvt

[Wang Yaduo]

Thanks for the detailed explanation.
> I think aarch64 works around that in the backend, detecting the gather
> scalar-load case and adjusting accordingly, but I'd rather have a vectorizer
> change. I'd hope we can land a vectorizer patch during stage 1. It might
> still make sense to open a riscv PR/bug on the side so we can fix the issue
> during stage3/4 in case the vectorizer patch doesn't land.
That makes a lot of sense. On a related note, are there other known 
performance-related 
TODOs on the RISC-V backend that you're aware of? I'd like to help where 
I can — would be great to know what areas could use attention.
Best regards,
Yaduo