On 5/27/2026 7:57 PM, Wang Yaduo wrote:
Thanks for the detailed explanation.
> I think aarch64 works around that in the backend, detecting the gather
> scalar-load case and adjusting accordingly, but I'd rather have a
vectorizer
> change. I'd hope we can land a vectorizer patch during stage 1. It might
> still make sense to open a riscv PR/bug on the side so we can fix
the issue
> during stage3/4 in case the vectorizer patch doesn't land.
That makes a lot of sense. On a related note, are there other known
performance-related
TODOs on the RISC-V backend that you're aware of? I'd like to help where
I can — would be great to know what areas could use attention.
All kinds :-) I think the question is what areas are you most
interested in working on?
In general Robin tends to focus mostly on the vector side and I focus on
the scalar side. Robin's got several in-flight efforts in the vector
space and can probably suggest one or more that are in need of developer
attention.
On the scalar side probably the biggest effort to push on would be
elimination of the various define_insn_and_splits. Those tend to
inhibit optimizations in fun and interesting ways and get in the way of
solving certain scalar problems in the most natural way.
jeff
