This series adds GCC support for the RISC-V Zvdota and Zvbdota families of vector dot-product extensions.
The Zvdota family computes a dot product between two vector register groups: - Zvqwdota8i: 8-bit integer -> 32-bit accumulation - Zvqwdota16i: 16-bit integer -> 64-bit accumulation - Zvfwdota16bf: bfloat16 -> 32-bit accumulation - Zvfqwdota8f: FP8 (E4M3/E5M2) -> 32-bit accumulation The Zvbdota family computes up to eight batched dot products at a time, using an EMUL=8 vs2 register group and a scaled ci immediate: - Zvqwbdota8i, Zvqwbdota16i, Zvfwbdota16bf, Zvfqwbdota8f, Zvfbdota32f The public intrinsic names follow the riscv-rvv-intrinsic-doc naming scheme, encoding VS2, VS1 and VD types in the suffix. The ISA-level split between the instruction mnemonic (selected from VS2) and vtype.altfmt (selected from VS1) is handled transparently by the backend. The FP32 vfbdota form follows the documented special case and uses only the destination type suffix. This series has been tested on riscv64-unknown-elf with no regressions in the RVV intrinsic testsuite. No auto-vectorizer support is included in this series. Jiawei Chen (4): RISC-V: Add minimal support for Zvdota and Zvbdota extension family RISC-V: Add machine patterns for Zvdota and Zvbdota instructions RISC-V: Add RVV intrinsics for Zvdota RISC-V: Add RVV intrinsics for Zvbdota
