Add RTL patterns for the Zvdota and Zvbdota dot-product
instructions. The patterns model the destructive accumulator operand
and use explicit altfmt operands where the runtime vtype.altfmt state
selects the VS1 interpretation. Zvbdota patterns also take a scaled
ci immediate operand.
gcc/ChangeLog:
* config/riscv/predicates.md (zvbdota_ci_operand): New operand.
* config/riscv/riscv-protos.h (enum mask_policy): Update altfmt
comment.
* config/riscv/riscv.md: Include vector-dot.md.
* config/riscv/vector-iterators.md: Add UNSPEC and iterator
definitions for Zvdota and Zvbdota.
* config/riscv/vector-dot.md: New file.
---
gcc/config/riscv/predicates.md | 5 +
gcc/config/riscv/riscv-protos.h | 5 +-
gcc/config/riscv/riscv.md | 1 +
gcc/config/riscv/vector-dot.md | 246 +++++++++++++++++++++++++++
gcc/config/riscv/vector-iterators.md | 207 ++++++++++++++++++++++
5 files changed, 461 insertions(+), 3 deletions(-)
create mode 100644 gcc/config/riscv/vector-dot.md
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index df1a76049f4..54fb5369c44 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -83,6 +83,11 @@
(and (match_code "const_int")
(match_test "IN_RANGE (INTVAL (op), 0, 10)")))
+(define_predicate "zvbdota_ci_operand"
+ (and (match_code "const_int")
+ (match_test "IN_RANGE (INTVAL (op), 0, 56)
+ && INTVAL (op) % 8 == 0")))
+
(define_predicate "csr_operand"
(ior (match_operand 0 "const_csr_operand")
(match_operand 0 "register_operand")))
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index fa360157570..a8a40f5dda9 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -663,9 +663,8 @@ enum mask_policy
/* Values for the VTYPE altfmt field. Instructions that do not care about
altfmt leave the "altfmt" insn attribute at its default (INVALID_ATTRIBUTE);
- FP8 instructions select between standard (ALTFMT_NONE, E4M3) and the
- alternate format (ALTFMT_ALT, E5M2) by setting the attribute via an
- operand. */
+ Some dot-product instructions select their vs1 interpretation by setting
+ the attribute via an operand. */
enum altfmt_type
{
ALTFMT_NONE = 0,
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 2055e5c4a9d..2cfa3772f3f 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -5261,6 +5261,7 @@
(include "vector.md")
(include "vector-crypto.md")
(include "vector-bfloat16.md")
+(include "vector-dot.md")
(include "zicond.md")
(include "mips-insn.md")
(include "sfb.md")
diff --git a/gcc/config/riscv/vector-dot.md b/gcc/config/riscv/vector-dot.md
new file mode 100644
index 00000000000..f2c84322f1f
--- /dev/null
+++ b/gcc/config/riscv/vector-dot.md
@@ -0,0 +1,246 @@
+;; Machine description for RISC-V vector dot-product extensions.
+;; Copyright (C) 2026 Free Software Foundation, Inc.
+;; Contributed by Jiawei Chen ([email protected]), ISCAS.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+;;
+;; Zvdota dot-product instructions
+;;
+
+(define_insn "@pred_<zvqwdot>_vv_zvdota<mode>"
+ [(set (match_operand:<ZVQWDOTI_ACC> 0 "register_operand" "=&vr")
+ (if_then_else:<ZVQWDOTI_ACC>
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1")
+ (match_operand 5 "vector_length_operand" "
rvl")
+ (match_operand 6 "const_int_operand" "
i")
+ (match_operand 7 "const_int_operand" "
i")
+ (match_operand 8 "const_int_operand" "
i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (unspec:<ZVQWDOTI_ACC>
+ [(match_operand:ZVQWDOTI_SRCMODE 3 "register_operand" "
vr")
+ (match_operand:ZVQWDOTI_SRCMODE 4 "register_operand" "
vr")
+ (match_operand:<ZVQWDOTI_ACC> 2 "register_operand" "
0")
+ (match_operand 9 "const_int_operand" "
i")]
+ ZVQWDOT)
+ (match_dup 2)))]
+ "TARGET_VECTOR"
+ "<zvqwdot>.vv\t%0,%3,%4%p1"
+ [(set_attr "type" "viwmuladd")
+ (set_attr "mode" "<MODE>")
+ (set_attr "merge_op_idx" "2")
+ (set_attr "vl_op_idx" "5")
+ (set (attr "ta") (symbol_ref "riscv_vector::get_ta (operands[6])"))
+ (set (attr "ma") (symbol_ref "riscv_vector::get_ma (operands[7])"))
+ (set (attr "avl_type_idx") (const_int 8))
+ (set (attr "altfmt")
+ (symbol_ref "INTVAL (operands[9])
+ ? riscv_vector::ALTFMT_ALT
+ : riscv_vector::ALTFMT_NONE"))])
+
+(define_insn "@pred_vfwdota_vv_zvdota<mode>"
+ [(set (match_operand:<ZVFWDOTBF_ACC> 0 "register_operand" "=&vr")
+ (if_then_else:<ZVFWDOTBF_ACC>
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1")
+ (match_operand 5 "vector_length_operand" "
rvl")
+ (match_operand 6 "const_int_operand" "
i")
+ (match_operand 7 "const_int_operand" "
i")
+ (match_operand 8 "const_int_operand" "
i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (unspec:<ZVFWDOTBF_ACC>
+ [(match_operand:ZVFWDOTBF_SRCMODE 3 "register_operand" "
vr")
+ (match_operand:ZVFWDOTBF_SRCMODE 4 "register_operand" "
vr")
+ (match_operand:<ZVFWDOTBF_ACC> 2 "register_operand" "
0")]
+ UNSPEC_VFWDOTA)
+ (match_dup 2)))]
+ "TARGET_VECTOR"
+ "vfwdota.vv\t%0,%3,%4%p1"
+ [(set_attr "type" "vfwmaccbf16")
+ (set_attr "mode" "<MODE>")
+ (set_attr "merge_op_idx" "2")
+ (set_attr "vl_op_idx" "5")
+ (set (attr "ta") (symbol_ref "riscv_vector::get_ta (operands[6])"))
+ (set (attr "ma") (symbol_ref "riscv_vector::get_ma (operands[7])"))
+ (set (attr "avl_type_idx") (const_int 8))
+ (set (attr "altfmt") (symbol_ref "riscv_vector::ALTFMT_ALT"))])
+
+(define_insn "@pred_<zvfqwdot>_vv_zvdota<mode>"
+ [(set (match_operand:<ZVFQWDOT8F_ACC> 0 "register_operand" "=&vr")
+ (if_then_else:<ZVFQWDOT8F_ACC>
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1")
+ (match_operand 5 "vector_length_operand" "
rvl")
+ (match_operand 6 "const_int_operand" "
i")
+ (match_operand 7 "const_int_operand" "
i")
+ (match_operand 8 "const_int_operand" "
i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (unspec:<ZVFQWDOT8F_ACC>
+ [(match_operand:ZVFQWDOT8F_SRCMODE 3 "register_operand" "
vr")
+ (match_operand:ZVFQWDOT8F_SRCMODE 4 "register_operand" "
vr")
+ (match_operand:<ZVFQWDOT8F_ACC> 2 "register_operand" "
0")
+ (match_operand 9 "const_int_operand" "
i")]
+ ZVFQWDOT)
+ (match_dup 2)))]
+ "TARGET_VECTOR"
+ "<zvfqwdot_asm>.vv\t%0,%3,%4%p1"
+ [(set_attr "type" "vfwmuladd")
+ (set_attr "mode" "<MODE>")
+ (set_attr "merge_op_idx" "2")
+ (set_attr "vl_op_idx" "5")
+ (set (attr "ta") (symbol_ref "riscv_vector::get_ta (operands[6])"))
+ (set (attr "ma") (symbol_ref "riscv_vector::get_ma (operands[7])"))
+ (set (attr "avl_type_idx") (const_int 8))
+ (set (attr "altfmt")
+ (symbol_ref "INTVAL (operands[9])
+ ? riscv_vector::ALTFMT_ALT
+ : riscv_vector::ALTFMT_NONE"))])
+
+;;
-------------------------------------------------------------------------------
+;; ---- Zvbdota batched dot-product instructions
+;;
-------------------------------------------------------------------------------
+
+(define_insn "@pred_<zvqwbdot>_vv<mode>"
+ [(set (match_operand:ZVQWBDOTI 0 "register_operand"
"=&vr")
+ (if_then_else:ZVQWBDOTI
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1")
+ (match_operand 6 "vector_length_operand" "
rvl")
+ (match_operand 7 "const_int_operand" "
i")
+ (match_operand 8 "const_int_operand" "
i")
+ (match_operand 9 "const_int_operand" "
i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (unspec:ZVQWBDOTI
+ [(match_operand:<ZVQWBDOTI_GROUP> 3 "register_operand" "
vr")
+ (match_operand:<ZVQWBDOTI_SRC> 4 "register_operand" "
vr")
+ (match_operand 5 "zvbdota_ci_operand" " i")
+ (match_operand:ZVQWBDOTI 2 "register_operand" "
0")
+ (match_operand 10 "const_int_operand" "
i")]
+ ZVQWBDOT)
+ (match_dup 2)))]
+ "TARGET_VECTOR"
+ "<zvqwbdot>.vv\t%0,%3,%4,%5%p1"
+ [(set_attr "type" "viwmuladd")
+ (set_attr "mode" "<ZVQWBDOTI_SRC>")
+ (set_attr "merge_op_idx" "2")
+ (set_attr "vl_op_idx" "6")
+ (set (attr "ta") (symbol_ref "riscv_vector::get_ta (operands[7])"))
+ (set (attr "ma") (symbol_ref "riscv_vector::get_ma (operands[8])"))
+ (set (attr "avl_type_idx") (const_int 9))
+ (set (attr "altfmt")
+ (symbol_ref "INTVAL (operands[10])
+ ? riscv_vector::ALTFMT_ALT
+ : riscv_vector::ALTFMT_NONE"))])
+
+(define_insn "@pred_vfwbdota_vv<mode>"
+ [(set (match_operand:ZVFWBDOTBF 0 "register_operand"
"=&vr")
+ (if_then_else:ZVFWBDOTBF
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1")
+ (match_operand 6 "vector_length_operand" "
rvl")
+ (match_operand 7 "const_int_operand" "
i")
+ (match_operand 8 "const_int_operand" "
i")
+ (match_operand 9 "const_int_operand" "
i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (unspec:ZVFWBDOTBF
+ [(match_operand:<ZVFWBDOTBF_GROUP> 3 "register_operand" "
vr")
+ (match_operand:<ZVFWBDOTBF_SRC> 4 "register_operand" "
vr")
+ (match_operand 5 "zvbdota_ci_operand" " i")
+ (match_operand:ZVFWBDOTBF 2 "register_operand" "
0")]
+ UNSPEC_VFWBDOTA)
+ (match_dup 2)))]
+ "TARGET_VECTOR"
+ "vfwbdota.vv\t%0,%3,%4,%5%p1"
+ [(set_attr "type" "vfwmaccbf16")
+ (set_attr "mode" "<ZVFWBDOTBF_SRC>")
+ (set_attr "merge_op_idx" "2")
+ (set_attr "vl_op_idx" "6")
+ (set (attr "ta") (symbol_ref "riscv_vector::get_ta (operands[7])"))
+ (set (attr "ma") (symbol_ref "riscv_vector::get_ma (operands[8])"))
+ (set (attr "avl_type_idx") (const_int 9))
+ (set (attr "altfmt") (symbol_ref "riscv_vector::ALTFMT_ALT"))])
+
+(define_insn "@pred_<zvfqwbdot>_vv<mode>"
+ [(set (match_operand:ZVFQWBDOT8F 0 "register_operand"
"=&vr")
+ (if_then_else:ZVFQWBDOT8F
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1")
+ (match_operand 6 "vector_length_operand" "
rvl")
+ (match_operand 7 "const_int_operand" "
i")
+ (match_operand 8 "const_int_operand" "
i")
+ (match_operand 9 "const_int_operand" "
i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ (unspec:ZVFQWBDOT8F
+ [(match_operand:<ZVFQWBDOT8F_GROUP> 3 "register_operand" "
vr")
+ (match_operand:<ZVFQWBDOT8F_SRC> 4 "register_operand" "
vr")
+ (match_operand 5 "zvbdota_ci_operand" " i")
+ (match_operand:ZVFQWBDOT8F 2 "register_operand" "
0")
+ (match_operand 10 "const_int_operand" "
i")]
+ ZVFQWBDOT)
+ (match_dup 2)))]
+ "TARGET_VECTOR"
+ "<zvfqwbdot_asm>.vv\t%0,%3,%4,%5%p1"
+ [(set_attr "type" "vfwmuladd")
+ (set_attr "mode" "<ZVFQWBDOT8F_SRC>")
+ (set_attr "merge_op_idx" "2")
+ (set_attr "vl_op_idx" "6")
+ (set (attr "ta") (symbol_ref "riscv_vector::get_ta (operands[7])"))
+ (set (attr "ma") (symbol_ref "riscv_vector::get_ma (operands[8])"))
+ (set (attr "avl_type_idx") (const_int 9))
+ (set (attr "altfmt")
+ (symbol_ref "INTVAL (operands[10])
+ ? riscv_vector::ALTFMT_ALT
+ : riscv_vector::ALTFMT_NONE"))])
+
+(define_insn "@pred_vfbdota_vv<mode>"
+ [(set (match_operand:ZVFBDOT32F 0 "register_operand"
"=&vr")
+ (if_then_else:ZVFBDOT32F
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "vector_mask_operand"
"vmWc1")
+ (match_operand 6 "vector_length_operand" "
rvl")
+ (match_operand 7 "const_int_operand" "
i")
+ (match_operand 8 "const_int_operand" "
i")
+ (match_operand 9 "const_int_operand" "
i")
+ (match_operand 10 "const_int_operand" "
i")
+ (reg:SI VL_REGNUM)
+ (reg:SI VTYPE_REGNUM)
+ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+ (unspec:ZVFBDOT32F
+ [(match_operand:<ZVFBDOT32F_GROUP> 3 "register_operand" "
vr")
+ (match_operand:<ZVFBDOT32F_SRC> 4 "register_operand" "
vr")
+ (match_operand 5 "zvbdota_ci_operand" " i")
+ (match_operand:ZVFBDOT32F 2 "register_operand" "
0")]
+ UNSPEC_VFBDOTA)
+ (match_dup 2)))]
+ "TARGET_VECTOR"
+ "vfbdota.vv\t%0,%3,%4,%5%p1"
+ [(set_attr "type" "vfmuladd")
+ (set_attr "mode" "<ZVFBDOT32F_SRC>")
+ (set_attr "merge_op_idx" "2")
+ (set_attr "vl_op_idx" "6")
+ (set (attr "ta") (symbol_ref "riscv_vector::get_ta (operands[7])"))
+ (set (attr "ma") (symbol_ref "riscv_vector::get_ma (operands[8])"))
+ (set (attr "avl_type_idx") (const_int 9))
+ (set (attr "frm_mode")
+ (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
diff --git a/gcc/config/riscv/vector-iterators.md
b/gcc/config/riscv/vector-iterators.md
index 62a1eb3fbc0..ff1f4f7314d 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -83,6 +83,18 @@
UNSPEC_VFFMA
+ UNSPEC_VQWDOTAU
+ UNSPEC_VQWDOTAS
+ UNSPEC_VFWDOTA
+ UNSPEC_VFQWDOTA
+ UNSPEC_VFQWDOTA_ALT
+ UNSPEC_VQWBDOTAU
+ UNSPEC_VQWBDOTAS
+ UNSPEC_VFWBDOTA
+ UNSPEC_VFQWBDOTA
+ UNSPEC_VFQWBDOTA_ALT
+ UNSPEC_VFBDOTA
+
UNSPEC_VFMAX
UNSPEC_VFMIN
@@ -1472,6 +1484,174 @@
(V512DF "riscv_vector::vls_mode_valid_p (V512DFmode) &&
TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
])
+(define_mode_iterator ZVQWDOTI_SRCMODE [
+ (RVVMF8QI "TARGET_ZVQWDOTA8I && TARGET_VECTOR_ELEN_64")
+ (RVVMF4QI "TARGET_ZVQWDOTA8I")
+ (RVVMF2QI "TARGET_ZVQWDOTA8I")
+ (RVVM1QI "TARGET_ZVQWDOTA8I")
+ (RVVM2QI "TARGET_ZVQWDOTA8I")
+ (RVVM4QI "TARGET_ZVQWDOTA8I")
+ (RVVM8QI "TARGET_ZVQWDOTA8I")
+
+ (RVVMF4HI "TARGET_ZVQWDOTA16I && TARGET_VECTOR_ELEN_64")
+ (RVVMF2HI "TARGET_ZVQWDOTA16I && TARGET_VECTOR_ELEN_64")
+ (RVVM1HI "TARGET_ZVQWDOTA16I && TARGET_VECTOR_ELEN_64")
+ (RVVM2HI "TARGET_ZVQWDOTA16I && TARGET_VECTOR_ELEN_64")
+ (RVVM4HI "TARGET_ZVQWDOTA16I && TARGET_VECTOR_ELEN_64")
+ (RVVM8HI "TARGET_ZVQWDOTA16I && TARGET_VECTOR_ELEN_64")
+])
+
+(define_mode_attr ZVQWDOTI_ACC [
+ (RVVMF8QI "RVVM1SI")
+ (RVVMF4QI "RVVM1SI")
+ (RVVMF2QI "RVVM1SI")
+ (RVVM1QI "RVVM1SI")
+ (RVVM2QI "RVVM1SI")
+ (RVVM4QI "RVVM1SI")
+ (RVVM8QI "RVVM1SI")
+
+ (RVVMF4HI "RVVM1DI")
+ (RVVMF2HI "RVVM1DI")
+ (RVVM1HI "RVVM1DI")
+ (RVVM2HI "RVVM1DI")
+ (RVVM4HI "RVVM1DI")
+ (RVVM8HI "RVVM1DI")
+])
+
+(define_mode_iterator ZVFWDOTBF_SRCMODE [
+ (RVVMF4BF "TARGET_ZVFWDOTA16BF && TARGET_VECTOR_ELEN_BF_16 &&
TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
+ (RVVMF2BF "TARGET_ZVFWDOTA16BF && TARGET_VECTOR_ELEN_BF_16 &&
TARGET_VECTOR_ELEN_FP_32")
+ (RVVM1BF "TARGET_ZVFWDOTA16BF && TARGET_VECTOR_ELEN_BF_16 &&
TARGET_VECTOR_ELEN_FP_32")
+ (RVVM2BF "TARGET_ZVFWDOTA16BF && TARGET_VECTOR_ELEN_BF_16 &&
TARGET_VECTOR_ELEN_FP_32")
+ (RVVM4BF "TARGET_ZVFWDOTA16BF && TARGET_VECTOR_ELEN_BF_16 &&
TARGET_VECTOR_ELEN_FP_32")
+ (RVVM8BF "TARGET_ZVFWDOTA16BF && TARGET_VECTOR_ELEN_BF_16 &&
TARGET_VECTOR_ELEN_FP_32")
+])
+
+(define_mode_attr ZVFWDOTBF_ACC [
+ (RVVMF4BF "RVVM1SF")
+ (RVVMF2BF "RVVM1SF")
+ (RVVM1BF "RVVM1SF")
+ (RVVM2BF "RVVM1SF")
+ (RVVM4BF "RVVM1SF")
+ (RVVM8BF "RVVM1SF")
+])
+
+(define_mode_iterator ZVFQWDOT8F_SRCMODE [
+ (RVVMF8QI "TARGET_ZVFQWDOTA8F && TARGET_VECTOR_ELEN_FP_32 &&
TARGET_VECTOR_ELEN_64")
+ (RVVMF4QI "TARGET_ZVFQWDOTA8F && TARGET_VECTOR_ELEN_FP_32")
+ (RVVMF2QI "TARGET_ZVFQWDOTA8F && TARGET_VECTOR_ELEN_FP_32")
+ (RVVM1QI "TARGET_ZVFQWDOTA8F && TARGET_VECTOR_ELEN_FP_32")
+ (RVVM2QI "TARGET_ZVFQWDOTA8F && TARGET_VECTOR_ELEN_FP_32")
+ (RVVM4QI "TARGET_ZVFQWDOTA8F && TARGET_VECTOR_ELEN_FP_32")
+ (RVVM8QI "TARGET_ZVFQWDOTA8F && TARGET_VECTOR_ELEN_FP_32")
+])
+
+(define_mode_attr ZVFQWDOT8F_ACC [
+ (RVVMF8QI "RVVM1SF")
+ (RVVMF4QI "RVVM1SF")
+ (RVVMF2QI "RVVM1SF")
+ (RVVM1QI "RVVM1SF")
+ (RVVM2QI "RVVM1SF")
+ (RVVM4QI "RVVM1SF")
+ (RVVM8QI "RVVM1SF")
+])
+
+(define_mode_iterator ZVQWBDOTI [
+ (RVVM1SI "TARGET_ZVQWBDOTA8I")
+ (RVVM2SI "TARGET_ZVQWBDOTA8I")
+ (RVVM4SI "TARGET_ZVQWBDOTA8I")
+ (RVVM8SI "TARGET_ZVQWBDOTA8I")
+ (RVVM1DI "TARGET_ZVQWBDOTA16I && TARGET_VECTOR_ELEN_64")
+ (RVVM2DI "TARGET_ZVQWBDOTA16I && TARGET_VECTOR_ELEN_64")
+ (RVVM4DI "TARGET_ZVQWBDOTA16I && TARGET_VECTOR_ELEN_64")
+ (RVVM8DI "TARGET_ZVQWBDOTA16I && TARGET_VECTOR_ELEN_64")
+])
+
+(define_mode_attr ZVQWBDOTI_SRC [
+ (RVVM1SI "RVVM1QI")
+ (RVVM2SI "RVVM1QI")
+ (RVVM4SI "RVVM1QI")
+ (RVVM8SI "RVVM1QI")
+ (RVVM1DI "RVVM1HI")
+ (RVVM2DI "RVVM1HI")
+ (RVVM4DI "RVVM1HI")
+ (RVVM8DI "RVVM1HI")
+])
+
+(define_mode_attr ZVQWBDOTI_GROUP [
+ (RVVM1SI "RVVM8QI")
+ (RVVM2SI "RVVM8QI")
+ (RVVM4SI "RVVM8QI")
+ (RVVM8SI "RVVM8QI")
+ (RVVM1DI "RVVM8HI")
+ (RVVM2DI "RVVM8HI")
+ (RVVM4DI "RVVM8HI")
+ (RVVM8DI "RVVM8HI")
+])
+
+(define_mode_iterator ZVFWBDOTBF [
+ (RVVM1SF "TARGET_ZVFWBDOTA16BF && TARGET_VECTOR_ELEN_BF_16 &&
TARGET_VECTOR_ELEN_FP_32")
+ (RVVM2SF "TARGET_ZVFWBDOTA16BF && TARGET_VECTOR_ELEN_BF_16 &&
TARGET_VECTOR_ELEN_FP_32")
+ (RVVM4SF "TARGET_ZVFWBDOTA16BF && TARGET_VECTOR_ELEN_BF_16 &&
TARGET_VECTOR_ELEN_FP_32")
+ (RVVM8SF "TARGET_ZVFWBDOTA16BF && TARGET_VECTOR_ELEN_BF_16 &&
TARGET_VECTOR_ELEN_FP_32")
+])
+
+(define_mode_attr ZVFWBDOTBF_SRC [
+ (RVVM1SF "RVVM1BF")
+ (RVVM2SF "RVVM1BF")
+ (RVVM4SF "RVVM1BF")
+ (RVVM8SF "RVVM1BF")
+])
+
+(define_mode_attr ZVFWBDOTBF_GROUP [
+ (RVVM1SF "RVVM8BF")
+ (RVVM2SF "RVVM8BF")
+ (RVVM4SF "RVVM8BF")
+ (RVVM8SF "RVVM8BF")
+])
+
+(define_mode_iterator ZVFQWBDOT8F [
+ (RVVM1SF "TARGET_ZVFQWBDOTA8F && TARGET_VECTOR_ELEN_FP_32")
+ (RVVM2SF "TARGET_ZVFQWBDOTA8F && TARGET_VECTOR_ELEN_FP_32")
+ (RVVM4SF "TARGET_ZVFQWBDOTA8F && TARGET_VECTOR_ELEN_FP_32")
+ (RVVM8SF "TARGET_ZVFQWBDOTA8F && TARGET_VECTOR_ELEN_FP_32")
+])
+
+(define_mode_attr ZVFQWBDOT8F_SRC [
+ (RVVM1SF "RVVM1QI")
+ (RVVM2SF "RVVM1QI")
+ (RVVM4SF "RVVM1QI")
+ (RVVM8SF "RVVM1QI")
+])
+
+(define_mode_attr ZVFQWBDOT8F_GROUP [
+ (RVVM1SF "RVVM8QI")
+ (RVVM2SF "RVVM8QI")
+ (RVVM4SF "RVVM8QI")
+ (RVVM8SF "RVVM8QI")
+])
+
+(define_mode_iterator ZVFBDOT32F [
+ (RVVM1SF "TARGET_ZVFBDOTA32F && TARGET_VECTOR_ELEN_FP_32")
+ (RVVM2SF "TARGET_ZVFBDOTA32F && TARGET_VECTOR_ELEN_FP_32")
+ (RVVM4SF "TARGET_ZVFBDOTA32F && TARGET_VECTOR_ELEN_FP_32")
+ (RVVM8SF "TARGET_ZVFBDOTA32F && TARGET_VECTOR_ELEN_FP_32")
+])
+
+(define_mode_attr ZVFBDOT32F_SRC [
+ (RVVM1SF "RVVM1SF")
+ (RVVM2SF "RVVM1SF")
+ (RVVM4SF "RVVM1SF")
+ (RVVM8SF "RVVM1SF")
+])
+
+(define_mode_attr ZVFBDOT32F_GROUP [
+ (RVVM1SF "RVVM8SF")
+ (RVVM2SF "RVVM8SF")
+ (RVVM4SF "RVVM8SF")
+ (RVVM8SF "RVVM8SF")
+])
+
(define_mode_iterator VOEXTI [
(RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
(RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
@@ -5430,6 +5610,14 @@
(define_int_iterator VFCVTS [UNSPEC_VFCVT UNSPEC_UNSIGNED_VFCVT])
+(define_int_iterator ZVQWDOT [UNSPEC_VQWDOTAU UNSPEC_VQWDOTAS])
+
+(define_int_iterator ZVFQWDOT [UNSPEC_VFQWDOTA UNSPEC_VFQWDOTA_ALT])
+
+(define_int_iterator ZVQWBDOT [UNSPEC_VQWBDOTAU UNSPEC_VQWBDOTAS])
+
+(define_int_iterator ZVFQWBDOT [UNSPEC_VFQWBDOTA UNSPEC_VFQWBDOTA_ALT])
+
(define_int_attr order [
(UNSPEC_ORDERED "o") (UNSPEC_UNORDERED "u")
(UNSPEC_REDUC_SUM_ORDERED "o") (UNSPEC_REDUC_SUM_UNORDERED "u")
@@ -5442,6 +5630,25 @@
(UNSPEC_VNCLIP "") (UNSPEC_VNCLIPU "u")
(UNSPEC_VFCVT "") (UNSPEC_UNSIGNED_VFCVT "u")
(UNSPEC_SF_VFNRCLIP "") (UNSPEC_SF_VFNRCLIPU "u")])
+
+(define_int_attr zvqwdot [(UNSPEC_VQWDOTAU "vqwdotau")
+ (UNSPEC_VQWDOTAS "vqwdotas")])
+
+(define_int_attr zvfqwdot [(UNSPEC_VFQWDOTA "vfqwdota")
+ (UNSPEC_VFQWDOTA_ALT "vfqwdota_alt")])
+
+(define_int_attr zvfqwdot_asm [(UNSPEC_VFQWDOTA "vfqwdota")
+ (UNSPEC_VFQWDOTA_ALT "vfqwdota.alt")])
+
+(define_int_attr zvqwbdot [(UNSPEC_VQWBDOTAU "vqwbdotau")
+ (UNSPEC_VQWBDOTAS "vqwbdotas")])
+
+(define_int_attr zvfqwbdot [(UNSPEC_VFQWBDOTA "vfqwbdota")
+ (UNSPEC_VFQWBDOTA_ALT "vfqwbdota_alt")])
+
+(define_int_attr zvfqwbdot_asm [(UNSPEC_VFQWBDOTA "vfqwbdota")
+ (UNSPEC_VFQWBDOTA_ALT "vfqwbdota.alt")])
+
(define_int_attr sat_op [(UNSPEC_VAADDU "aaddu") (UNSPEC_VAADD "aadd")
(UNSPEC_VASUBU "asubu") (UNSPEC_VASUB "asub")
(UNSPEC_VSMUL "smul") (UNSPEC_VSSRL "ssrl")
--
2.43.0
