在 2026/6/16 3:30, Robin Dapp 写道:
+(define_mode_iterator ZVQWDOTI_SRCMODE [
+ (RVVMF8QI "TARGET_ZVQWDOTA8I && TARGET_VECTOR_ELEN_64")
+ (RVVMF4QI "TARGET_ZVQWDOTA8I")
+ (RVVMF2QI "TARGET_ZVQWDOTA8I")
+ (RVVM1QI "TARGET_ZVQWDOTA8I")
+ (RVVM2QI "TARGET_ZVQWDOTA8I")
+ (RVVM4QI "TARGET_ZVQWDOTA8I")
+ (RVVM8QI "TARGET_ZVQWDOTA8I")
+
+ (RVVMF4HI "TARGET_ZVQWDOTA16I && TARGET_VECTOR_ELEN_64")
+ (RVVMF2HI "TARGET_ZVQWDOTA16I && TARGET_VECTOR_ELEN_64")
+ (RVVM1HI "TARGET_ZVQWDOTA16I && TARGET_VECTOR_ELEN_64")
+ (RVVM2HI "TARGET_ZVQWDOTA16I && TARGET_VECTOR_ELEN_64")
+ (RVVM4HI "TARGET_ZVQWDOTA16I && TARGET_VECTOR_ELEN_64")
+ (RVVM8HI "TARGET_ZVQWDOTA16I && TARGET_VECTOR_ELEN_64")
+])
I think these are special cases of VQEXTI or V_QUAD_TRUNC. Can they be reused?
+
+(define_mode_attr ZVQWDOTI_ACC [
+ (RVVMF8QI "RVVM1SI")
+ (RVVMF4QI "RVVM1SI")
+ (RVVMF2QI "RVVM1SI")
+ (RVVM1QI "RVVM1SI")
+ (RVVM2QI "RVVM1SI")
+ (RVVM4QI "RVVM1SI")
+ (RVVM8QI "RVVM1SI")
+
+ (RVVMF4HI "RVVM1DI")
+ (RVVMF2HI "RVVM1DI")
+ (RVVM1HI "RVVM1DI")
+ (RVVM2HI "RVVM1DI")
+ (RVVM4HI "RVVM1DI")
+ (RVVM8HI "RVVM1DI")
+])
The naming doesn't really help understanding. I'd rather call the
iterators/attributes by their properties rather than the instruction they
belong to. In this case we already have V_EXT_LMUL1 for widening reductions.
So something like V_EXT2X_LMUL1 might work.
Hi Robin,
Thanks, that makes sense.
The current ZVQWDOTI_* names were chosen while bringing up the patterns,
but I agree that they describe the instruction rather than the mode
property. I will check whether the existing VQEXTI / V_QUAD_TRUNC
iterators cover the exact source-mode set needed here and reuse them if
possible.
For the accumulator mapping, the property I need is a source mode whose
dot-product accumulator mode is fixed at LMUL=1, e.g. QI -> SI m1 and
HI -> DI m1. If there is no existing iterator/attribute that matches
that exactly, I will rename the new iterator/attribute to something
property-based, along the lines of V_EXT2X_LMUL1 as you suggested, rather
than keeping the ZVQWDOTI_* names.
I will also make the extension predicates more explicit in the pattern
conditions, so that the define_insn conditions do not just read as
TARGET_VECTOR.
BR,
Jiawei
