On Wed, Aug 26, 2026 at 4:25 AM Roger Sayle <[email protected]> wrote:
>
>
> Alas this patch causes a single regression: avx10_2-vmovd-1.c.
> AVX 10.2's vmovd (like pslldq+psrldq) can also be used to perform
> {x[0],0,0,0}. I was hoping Hongtao, Uros or HJ, can suggest the
> right way to allow reload to select the most appropriate form for
> the target ISA.
I think you can just emit vmovd\t{%1, %0|%0, %1} from perm_0 when
INTVAL (operands[3]) == 0 && TARGET_AVX10_2,
+(define_insn "*sse4_1_insertps_<mode>_perm_1"
+ [(set (match_operand:VI4F_128 0 "register_operand" "=x,v")
+ (vec_select:VI4F_128
+ (vec_concat:<ssedoublevecmode>
+ (match_operand:VI4F_128 1 "register_operand" "0,v")
+ (match_operand:VI4F_128 2 "const0_operand"))
+ (parallel [(const_int 4)
+ (match_operand:SI 3 "const_0_to_3_operand")
+ (const_int 6)
+ (const_int 7)])))]
+ "TARGET_SSE4_1"
+{
+ operands[3] = GEN_INT ((INTVAL (operands[3]) << 6) + (32 + 13));
Should it be (16 + 13), not (32 + 13), similar for perm_2 (32 + 11),
perm_3 (48 + 7)?
According to SMD:
IF (SRC = REG) THEN COUNT_S := imm8[7:6]
ELSE COUNT_S := 0
COUNT_D := imm8[5:4]
ZMASK := imm8[3:0]
so INTVAL (operands[3]) << 6) is correct, 13 is correct, but count_d
is imm[5:4], should be << 4 which is 16, not 32.
┌─────────┬─────────┬─────────┬─────────────────────┬────────────────────────┐
│ pattern │ dst elt │ count_d │ zmask = 15 ^ (1<<d) │ term
│
├─────────┼─────────┼─────────┼─────────────────────┼────────────────────────┤
│ perm_0 │ 0 │ 0 │ 14 │ + 14 (already
correct) │
├─────────┼─────────┼─────────┼─────────────────────┼────────────────────────┤
│ perm_1 │ 1 │ 16 │ 13 │ + (16 + 13) = 29
│
├─────────┼─────────┼─────────┼─────────────────────┼────────────────────────┤
│ perm_2 │ 2 │ 32 │ 11 │ + (32 + 11) = 43
│
├─────────┼─────────┼─────────┼─────────────────────┼────────────────────────┤
│ perm_3 │ 3 │ 48 │ 7 │ + (48 + 7) = 55
│
└─────────┴─────────┴─────────┴─────────────────────┴────────────────────────┘
--
BR,
Hongtao
