On Wed, Sep 2, 2026 at 8:21 PM Roger Sayle <[email protected]> wrote:
>
>
> Hi Hongtao,
> Very many thanks for the review/feedback, and great catch on my
> mistake with the insertps immediate encoding. This revised patch
> implements all of your suggested changes (fixing the regression of
> avx10_2-vmovd-1.c) and I've also added execution tests to confirm
> the correct encoding on sse4.1, and also with the default/prevailing
> options.
>
> This patch has been tested on x86_64-pc-linux-gnu with make bootstrap
> and make -k check, both with and without --target_board=unix{-m32}
> with no new failures. Ok for mainline?
>
>
+ (parallel [(match_operand:SI 3 "const_0_to_3_operand")
+ (const_int 5)
+ (const_int 6)
+ (const_int 7)])))]
+ "TARGET_SSE4_1"
We can use const_4_to_7_operand instead of hard-coded const_int 5,
const_int 6, const_int 7 since they are equivalent const0.
.i.e below testcase still generate pxor + 2 shufps, but it should
generate insertps as your i21 in your new test(0, x[2], 0, 0)
typedef int v4si __attribute__((vector_size(16)));
v4si
foo (v4si x)
{
return __builtin_shuffle (x, (v4si){0, 0, 0, 0}, (v4si){7, 2, 4, 5});
}
So either replace them with const_4_to_7 for all three patterns in the
parallel or maybe just define an new match_parallel predicate for
them(.i.e pmovzx_parallel)
>
>
> Thanks again.
> Roger
> --
>
> > -----Original Message-----
> > From: Hongtao Liu <[email protected]>
> > Sent: 26 August 2026 07:42
> > To: Roger Sayle <[email protected]>
> > Cc: Patches GCC <[email protected]>; Liu, Hongtao
> > <[email protected]>; Uros Bizjak <[email protected]>
> > Subject: Re: [x86 SSE PATCH] More uses of insertps to implement
> > VEC_PERM_EXPR.
> >
> > On Wed, Aug 26, 2026 at 4:25 AM Roger Sayle <[email protected]>
> > wrote:
> >
> > > Alas this patch causes a single regression: avx10_2-vmovd-1.c.
> > > AVX 10.2's vmovd (like pslldq+psrldq) can also be used to perform
> > > {x[0],0,0,0}. I was hoping Hongtao, Uros or HJ, can suggest the right
> > > way to allow reload to select the most appropriate form for the target
> > > ISA.
> > I think you can just emit vmovd\t{%1, %0|%0, %1} from perm_0 when INTVAL
> > (operands[3]) == 0 && TARGET_AVX10_2,
> >
> > +(define_insn "*sse4_1_insertps_<mode>_perm_1"
> > + [(set (match_operand:VI4F_128 0 "register_operand" "=x,v")
> > + (vec_select:VI4F_128
> > + (vec_concat:<ssedoublevecmode>
> > + (match_operand:VI4F_128 1 "register_operand" "0,v")
> > + (match_operand:VI4F_128 2 "const0_operand"))
> > + (parallel [(const_int 4)
> > + (match_operand:SI 3 "const_0_to_3_operand")
> > + (const_int 6)
> > + (const_int 7)])))]
> > + "TARGET_SSE4_1"
> > +{
> > + operands[3] = GEN_INT ((INTVAL (operands[3]) << 6) + (32 + 13));
> >
> > Should it be (16 + 13), not (32 + 13), similar for perm_2 (32 + 11),
> > perm_3 (48 + 7)?
> >
> > According to SMD:
> > IF (SRC = REG) THEN COUNT_S := imm8[7:6]
> > ELSE COUNT_S := 0
> > COUNT_D := imm8[5:4]
> > ZMASK := imm8[3:0]
> >
> > so INTVAL (operands[3]) << 6) is correct, 13 is correct, but count_d is
> > imm[5:4],
> > should be << 4 which is 16, not 32.
> >
> > ┌─────────┬─────────┬─────────┬─────────────────────┬────────
> > ────────────────┐
> > │ pattern │ dst elt │ count_d │ zmask = 15 ^ (1<<d) │ term
> > │
> > ├─────────┼─────────┼─────────┼─────────────────────┼───────
> > ─────────────────┤
> > │ perm_0 │ 0 │ 0 │ 14 │ + 14 (already
> > correct) │
> > ├─────────┼─────────┼─────────┼─────────────────────┼───────
> > ─────────────────┤
> > │ perm_1 │ 1 │ 16 │ 13 │ + (16 + 13) = 29
> > │
> > ├─────────┼─────────┼─────────┼─────────────────────┼───────
> > ─────────────────┤
> > │ perm_2 │ 2 │ 32 │ 11 │ + (32 + 11) = 43
> > │
> > ├─────────┼─────────┼─────────┼─────────────────────┼───────
> > ─────────────────┤
> > │ perm_3 │ 3 │ 48 │ 7 │ + (48 + 7) = 55
> > │
> > └─────────┴─────────┴─────────┴─────────────────────┴────────
> > ────────────────┘
> >
> > --
> > BR,
> > Hongtao
--
BR,
Hongtao
