> From: Kumar, Venkataramanan <[email protected]>
> Sent: Friday, August 28, 2026 1:03 AM
>
> > From: Haochen Jiang <[email protected]>
> > Sent: Wednesday, August 19, 2026 11:19 AM
>
> What about adding runtime tests for cvtrow* patterns?
> They should get tested under targets having ACEV1 and no AMX-AVX512.
I suppose runtime test are not needed since they are redundant with
the same behavior.
We already have compile test to make sure it is correctly generated.
> >
> > gcc/ChangeLog:
> >
> > * config/i386/acev1intrin.h: Add new intrins.
> > * config/i386/i386-builtin-types.def: Add new builtin types.
> > * config/i386/i386-builtin.def (BDESC): Handle new builtins.
> > * config/i386/i386-expand.cc
> > (ix86_expand_ace_builtin): Handle new builtin type.
> > * config/i386/sse.md (UNSPEC_TCVTROWD2PS) New.
> > (UNSPEC_TCVTROWPS2FP16H): Ditto.
> > (UNSPEC_TCVTROWPS2FP16L): Ditto.
> > (UNSPEC_TILEMOVROWEXTRACT): Ditto.
> > (UNSPECV_TILEMOVROWINSERT): Ditto.
> > (UNSPECV_TILEMOVCOLINSERT): Ditto.
> > (VHFBF_512): Ditto.
> > (tcvtrowd2ps): Ditto.
> > (tcvtrowps2<bf16_ph><highlowsuffix>): Ditto.
> > (tilemovrow_extract): Ditto.:
> Remove :
> > (tilemov<rowcol>_insert): Ditto.
This is actually added in patterns?
> >
> > diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-
> expand.cc
> > index b6e5180564a..e9bc4a7d8e6 100644
> > --- a/gcc/config/i386/i386-expand.cc
> > +++ b/gcc/config/i386/i386-expand.cc
> > @@ -14732,9 +14744,20 @@ ix86_expand_ace_builtin (const struct
> > builtin_description *d, tree exp)
> >
> > gcc_assert (nargs <= ARRAY_SIZE (xops));
> >
> > + if (tmm_src)
> > + {
> > + machine_mode tmode = insn_p->operand[0].mode;
> > + arg_adjust = 1;
> > + if (optimize
> > + || target == 0
> > + || !register_operand (target, tmode)
> > + || GET_MODE (target) != tmode)
> > + target = gen_reg_rtx (tmode);
> > + }
>
> Why are we creating register always when optimize is set ??
When optimize is set, we want it directly to use register.
>
> > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index
> > e0e19a2d128..6f3bf44b557 100644
> > --- a/gcc/config/i386/sse.md
> > +++ b/gcc/config/i386/sse.md
> > @@ -34994,3 +35001,60 @@
> > "TARGET_ACEV1"
> > "bsrmovl\t{%1, %0|%0, %1}"
> > [(set_attr "prefix" "evex")])
> > +
> > +(define_insn "tcvtrowd2ps"
> > + [(set (match_operand:V16SF 0 "register_operand" "=v")
> > + (unspec:V16SF
> > + [(reg:V32SI TMM_REGNUM)
> > + (match_operand:QI 1 "const_0_to_7_operand")
> > + (match_operand:SI 2 "nonmemory_operand" "rN")]
>
> Is it left for the user to make sure he is not providing incorrect row index??
The least 4 bit is considered according to documentation. So, this needs
to be SI. Those are valid input.
>
> > + UNSPEC_TCVTROWD2PS))]
> > + "TARGET_ACEV1"
> > + "tcvtrowd2ps\t{%2, %%tmm%c1, %0|%0, tmm%c1, %2}"
> > + [(set_attr "prefix" "evex")])
> > +
> > +(define_int_iterator UNSPEC_TCVTROWPS2FP16TYPE
> > + [UNSPEC_TCVTROWPS2FP16H UNSPEC_TCVTROWPS2FP16L])
> > +
> > +(define_int_attr highlowsuffix
> > + [(UNSPEC_TCVTROWPS2FP16H "h") (UNSPEC_TCVTROWPS2FP16L "l")])
> > +
> > +(define_insn "tcvtrowps2<bf16_ph><highlowsuffix>"
> > + [(set (match_operand:VHFBF_512 0 "register_operand" "=v")
> > + (unspec:VHFBF_512
> > + [(reg:V32SF TMM_REGNUM)
>
> Mode of TMM register is V32SF in one place and V32SI in another place.
The V32SF is done on purpose here since the original src is ps, which is SF.
>
> > + (match_operand:QI 1 "const_0_to_7_operand")
> > + (match_operand:SI 2 "nonmemory_operand" "rN")]
> > + UNSPEC_TCVTROWPS2FP16TYPE))]
> > + "TARGET_ACEV1"
> > + "tcvtrowps2<bf16_ph><highlowsuffix>\t{%2, %%tmm%c1, %0|%0,
> > tmm%c1, %2}"
> > + [(set_attr "prefix" "evex")])
Thx,
Haochen
