[PATCH v1 1/4] RISC-V: Allow RVV register overlap for vfw{add, sub, mul}.vv

[pan2 . li]

From: Pan Li <pan2...@intel.com>

Like vw{add,sub,mul}[u].vv, allow the rvv register overlap for the
dual widen float vv insns, aka vfwadd.vv, vfwsub.vv and vfwmul.vv.

gcc/ChangeLog:

        * config/riscv/vector.md: Leverage Wvr constraint.

Signed-off-by: Pan Li <pan2...@intel.com>
---
 gcc/config/riscv/vector.md | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 023668ceada..37f7b94604d 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7292,24 +7292,24 @@ (define_insn "@pred_class<mode>"
 
 ;; Vector Widening Add/Subtract/Multiply.
 (define_insn "@pred_dual_widen_<optab><mode>"
-  [(set (match_operand:VWEXTF 0 "register_operand"                  "=&vr,  
&vr")
+  [(set (match_operand:VWEXTF 0 "register_operand"                 "=vr, vr, 
vd, vd")
        (if_then_else:VWEXTF
          (unspec:<VM>
-           [(match_operand:<VM> 1 "vector_mask_operand"           
"vmWc1,vmWc1")
-            (match_operand 5 "vector_length_operand"              "  rvl,  
rvl")
-            (match_operand 6 "const_int_operand"                  "    i,    
i")
-            (match_operand 7 "const_int_operand"                  "    i,    
i")
-            (match_operand 8 "const_int_operand"                  "    i,    
i")
-            (match_operand 9 "const_int_operand"                  "    i,    
i")
+           [(match_operand:<VM> 1 "vector_mask_operand"           "Wc1,Wc1, 
vm, vm")
+            (match_operand 5 "vector_length_operand"              
"rvl,rvl,rvl,rvl")
+            (match_operand 6 "const_int_operand"                  "  i,  i,  
i,  i")
+            (match_operand 7 "const_int_operand"                  "  i,  i,  
i,  i")
+            (match_operand 8 "const_int_operand"                  "  i,  i,  
i,  i")
+            (match_operand 9 "const_int_operand"                  "  i,  i,  
i,  i")
             (reg:SI VL_REGNUM)
             (reg:SI VTYPE_REGNUM)
             (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
          (any_widen_binop:VWEXTF
            (float_extend:VWEXTF
-             (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "   vr,   
vr"))
+             (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" 
"Wvr,Wvr,Wvr,Wvr"))
            (float_extend:VWEXTF
-             (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "   vr,   
vr")))
-         (match_operand:VWEXTF 2 "vector_merge_operand"           "   vu,    
0")))]
+             (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" 
"Wvr,Wvr,Wvr,Wvr")))
+         (match_operand:VWEXTF 2 "vector_merge_operand"           " vu,  0, 
vu,  0")))]
   "TARGET_VECTOR"
   "vfw<insn>.vv\t%0,%3,%4%p1"
   [(set_attr "type" "vf<widen_binop_insn_type>")
-- 
2.43.0