> Like vw{add,sub,mul}[u].vv, allow the rvv register overlap for the
> dual widen float vv insns, aka vfwadd.vv, vfwsub.vv and vfwmul.vv.LGTM. -- Regards Robin
- [PATCH v1 0/4] RISC-V: Allow RVV register overlap for vfw{add, ... pan2 . li
- [PATCH v1 1/4] RISC-V: Allow RVV register overlap for vfw{... pan2 . li
- Re: [PATCH v1 1/4] RISC-V: Allow RVV register overlap ... Robin Dapp
- [PATCH v1 2/4] RISC-V: Add test cases for vfwadd.vv reg ov... pan2 . li
- [PATCH v1 3/4] RISC-V: Add test cases for vfwsub.vv reg ov... pan2 . li
- [PATCH v1 4/4] RISC-V: Add test cases for vfwmul.vv reg ov... pan2 . li
