On Tue, Oct 13, 2026 at 8:40 PM Takayuki 'January June' Suwa <[email protected]> wrote: > On 2026/10/12 22:44, Max Filippov wrote: > (snip) > > @@ -1577,17 +1607,25 @@ > > "register_operand (operands[0], DFmode) > > || register_operand (operands[1], DFmode)" > > {@ [cons: =0, 1; attrs: type, length] > > - [a, r; move, 6] # > > - [a, Y; load, 6] ^ > > - [W, iF; move, 12] ^ > > - [a, T; load, 6] ^ > > - [a, U; load, 6] ^ > > - [U, r; store, 6] ^ > > + [f, Gc; farith, 3] const.d\t%0, %G1 > > + [f, r; farith, 3] wfrd\t%0, %T1, %B1 > > + [a, f; farith, 6] rfrd\t%T0, %1\;rfr\t%B0, %1 > > + [f, f; farith, 3] mov.d\t%0, %1 > > + [f, U; fload , 3] %v1ldi\t%0, %1 > > + [U, f; fstore, 3] %v0sdi\t%1, %0 > > + [a, r; move , 6] df-move-a-from-r\t%0, %1 > > + [a, Y; load , 6] df-load-a-from-Y\t%0, %1 > > + [a, T; load , 6] df-load-a-from-T\t%0, %1 > > + [a, U; load , 6] df-load-a-from-U\t%0, %1 > > + [U, r; store , 6] df-store-r-to-U\t%0, %1 > > }(snip) > > I understand that the LDI and SDI instructions belong to the fload and fstore > insn types, respectively; however, wouldn't their execution cycles differ > from those of their SFmode counterparts — LSI and SSI?
I can't find the actual numbers in the docs. Cycle-accurate simulation shows the same number of cycles for single and double precision loads and stores. My impression has always been that DFPU requires at least 64bit wide data bus, which means that load or store may go as a single transaction. I'll try to get some clarification. > It seems that these instructions need another insn type (eg., fload2 or > fstore2) that shares properties with fload or fstore but has a larger > execution cycle. I'll take a look, thanks for bringing it up. -- Thanks. -- Max
