On Wed, Oct 14, 2026 at 10:43 AM Takayuki 'January June' Suwa
<[email protected]> wrote:
> Regarding the point that double-precision load/store instructions for H/W FP
> registers are performed as a single transaction: does this also apply to the
> IRAM/IROM regions?
FP loads cannot be done over the instruction bus, l32r and l32i are
the only instructions that can do that.
> For example, out of the three possible results of compiling the following:
>
> void test(double a[]) {
> a[0] = a[127];
> a[1] = 3.1415926535897932384626433832795;
> }
>
> which one would be optimal?
again, cycle-accurate simulation shows that the last one is one
cycle shorter than the other two. But that's in an assumption that
literals are reachable over the data bus.
> # candidate #1
> .literal_position
> .literal .LC3, 1413754136
> .literal .LC4, 1074340347
> test:
> entry sp, 32
> l32r a8, .LC3
> l32r a9, .LC4
> ldi f0, a2, 1016
> wfrd f1, a9, a8
> sdi f0, a2, 0
> sdi f1, a2, 8
> retw.n
>
> # candidate #2
> .literal_position
> .literal .LC3, 1413754136
> .literal .LC4, 1074340347
> test:
> entry sp, 32
> ldi f0, a2, 1016
> l32r a8, .LC3
> l32r a9, .LC4
> sdi f0, a2, 0
> s32i.n a8, a2, 8
> s32i.n a9, a2, 12
> retw.n
>
> # candidate #3
> .literal_position
> .literal .LC0, 0x54442d18, 0x400921fb
> .literal .LC1, .LC0
> test:
> entry sp, 32
> l32r a8, .LC1
> ldi f0, a2, 1016
> ldi f1, a8, 0
> sdi f0, a2, 0
> sdi f1, a2, 8
> retw.n
>
--
Thanks.
-- Max
