Hi Max,
On 2026/10/15 0:14, Max Filippov wrote:
I understand that the LDI and SDI instructions belong to the fload and fstore
insn types, respectively; however, wouldn't their execution cycles differ from
those of their SFmode counterparts — LSI and SSI?
I can't find the actual numbers in the docs. Cycle-accurate simulation
shows the same number of cycles for single and double precision
loads and stores. My impression has always been that DFPU requires
at least 64bit wide data bus, which means that load or store may
go as a single transaction. I'll try to get some clarification.
It seems that these instructions need another insn type (eg., fload2 or
fstore2) that shares properties with fload or fstore but has a larger execution
cycle.
I'll take a look, thanks for bringing it up.
Regarding the point that double-precision load/store instructions for H/W FP
registers are performed as a single transaction: does this also apply to the
IRAM/IROM regions?
For example, out of the three possible results of compiling the following:
void test(double a[]) {
a[0] = a[127];
a[1] = 3.1415926535897932384626433832795;
}
which one would be optimal?
# candidate #1
.literal_position
.literal .LC3, 1413754136
.literal .LC4, 1074340347
test:
entry sp, 32
l32r a8, .LC3
l32r a9, .LC4
ldi f0, a2, 1016
wfrd f1, a9, a8
sdi f0, a2, 0
sdi f1, a2, 8
retw.n
# candidate #2
.literal_position
.literal .LC3, 1413754136
.literal .LC4, 1074340347
test:
entry sp, 32
ldi f0, a2, 1016
l32r a8, .LC3
l32r a9, .LC4
sdi f0, a2, 0
s32i.n a8, a2, 8
s32i.n a9, a2, 12
retw.n
# candidate #3
.literal_position
.literal .LC0, 0x54442d18, 0x400921fb
.literal .LC1, .LC0
test:
entry sp, 32
l32r a8, .LC1
ldi f0, a2, 1016
ldi f1, a8, 0
sdi f0, a2, 0
sdi f1, a2, 8
retw.n
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