From: "Sun, Qin" <[email protected]>
Add Razor Lake as an alias of Nova Lake since they have the same
feature set.
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (get_intel_cpu): Add Razor Lake
according to family/model settings.
* common/config/i386/i386-common.cc: Add razorlake.
* doc/invoke.texi: Add razorlake documentation.
---
gcc/common/config/i386/cpuinfo.h | 5 +++++
gcc/common/config/i386/i386-common.cc | 2 ++
gcc/doc/invoke.texi | 16 ++++++++--------
3 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index 3346d191cf3..5febcdb9b75 100644
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -709,6 +709,11 @@ get_intel_cpu (struct __processor_model *cpu_model,
case 0x01:
case 0x03:
/* Nova Lake. */
+ case 0x06:
+ case 0x07:
+ case 0x09:
+ case 0x0a:
+ /* Razor Lake. */
cpu = "novalake";
CHECK___builtin_cpu_is ("corei7");
CHECK___builtin_cpu_is ("novalake");
diff --git a/gcc/common/config/i386/i386-common.cc
b/gcc/common/config/i386/i386-common.cc
index a0bab45900b..c368f5040ba 100644
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -2520,6 +2520,8 @@ const pta processor_alias_table[] =
M_CPU_SUBTYPE (INTEL_COREI7_PANTHERLAKE), P_PROC_AVX2},
{"novalake", PROCESSOR_NOVALAKE, CPU_HASWELL, PTA_NOVALAKE,
M_CPU_SUBTYPE (INTEL_COREI7_NOVALAKE), P_PROC_AVX10_2},
+ {"razorlake", PROCESSOR_NOVALAKE, CPU_HASWELL, PTA_NOVALAKE,
+ M_CPU_SUBTYPE (INTEL_COREI7_NOVALAKE), P_PROC_AVX10_2},
{"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
{"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index cc2a62b7304..44f469caf8b 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -35432,14 +35432,14 @@ AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD,
AVXVNNIINT16, SHA512, SM3 and
SM4 instruction set support.
@item novalake
-Intel Nova Lake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
-SSSE3, SSE4.1, SSE4.2, POPCNT, CX16,
-AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC,
-XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI,
-MOVDIR64B, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, PCONFIG, PKU,
-VAES, VPCLMULQDQ, SERIALIZE, HRESET, AVX-VNNI, UINTR, AVXIFMA, AVXVNNIINT8,
-AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3, SM4, PREFETCHI, APX_F,
-AVX10.1, AVX10.2 and MOVRS instruction set support.
+@itemx razorlake
+Intel Nova Lake/Razor Lake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
+SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, AES, PREFETCHW, PCLMUL, RDRND,
+XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB,
+MOVDIRI, MOVDIR64B, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT,
+PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, AVX-VNNI, UINTR, AVXIFMA,
+AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3, SM4,
+PREFETCHI, APX_F, AVX10.1, AVX10.2 and MOVRS instruction set support.
@item sapphirerapids
@itemx emeraldrapids
--
2.31.1
