gcc/ChangeLog:
* common/config/i386/cpuinfo.h
(get_available_features): Add AVX10VPMLDSABFLYDQ.
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_AVX10VPMLDSABFLYDQ_SET): New.
(OPTION_MASK_ISA2_AVX10_2_UNSET): Add AVX10VPMLDSABFLYDQ.
(OPTION_MASK_ISA2_AVX10VPMLDSABFLYDQ_UNSET): New.
(ix86_handle_option): Handle avx10vpmldsabflydq.
* common/config/i386/i386-cpuinfo.h
(enum processor_features): Add FEATURE_AVX10VPMLDSABFLYDQ.
* common/config/i386/i386-isas.h: Ditto.
* config.gcc: Include avx10vpmldsabflydqintrin.h.
* config/i386/cpuid.h (bit_AVX10VPMLDSABFLYDQ): New.
* config/i386/i386-builtin-types.def: Define
V8SI_FTYPE_V8SI_V8SI_V8SI_INT and
V16SI_FTYPE_V16SI_V16SI_V16SI_INT.
* config/i386/i386-builtin.def
(BDESC): Handle AVX10VPMLDSABFLYDQ builtins.
* config/i386/i386-c.cc
(ix86_target_macros_internal): Handle AVX10VPMLDSABFLYDQ.
* config/i386/i386-expand.cc
(ix86_expand_args_builtin):
Handle V8SI_FTYPE_V8SI_V8SI_V8SI_INT and
V16SI_FTYPE_V16SI_V16SI_V16SI_INT.
* config/i386/i386-isa.def (AVX10VPMLDSABFLYDQ): New.
* config/i386/i386-options.cc (isa2_opts): Handle mavx10vpmldsabflydq.
(ix86_valid_target_attribute_inner_p): Ditto.
* config/i386/i386.opt: Add AVX10VPMLDSABFLYDQ.
* config/i386/i386.opt.urls: Ditto.
* config/i386/immintrin.h: Include avx10vpmldsabflydqintrin.h
* config/i386/sse.md (UNSPEC_VPMLDSABFLYDQ): New.
(avx10_2_vpmldsabflydq<mode>): Ditto.
* doc/extend.texi: Add avx10vpmldsabflydq documentation.
* doc/invoke.texi: Ditto.
* doc/sourcebuild.texi: Ditto.
* config/i386/avx10vpmldsabflydqintrin.h: New file.
gcc/testsuite/ChangeLog:
* g++.dg/other/i386-2.C: Add avx10vpmldsabflydq test.
* g++.dg/other/i386-3.C: Ditto.
* gcc.target/i386/avx-1.c: Ditto.
* gcc.target/i386/sse-12.c: Ditto.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Ditto.
* gcc.target/i386/sse-23.c: Ditto.
* gcc.target/i386/avx10-check.h: Ditto.
* gcc.target/i386/funcspec-56.inc: Ditto.
* lib/target-supports.exp
(check_effective_target_avx10vpmldsabflydq): New.
* gcc.target/i386/avx10vpmldsabflydq-1.c: New test.
* gcc.target/i386/avx10vpmldsabflydq-2.c: Ditto.
* gcc.target/i386/avx10vpmldsabflydq-2.h: Ditto.
* gcc.target/i386/avx10vpmldsabflydq-helper.h: Ditto.
---
gcc/common/config/i386/cpuinfo.h | 2 +
gcc/common/config/i386/i386-common.cc | 25 ++-
gcc/common/config/i386/i386-cpuinfo.h | 1 +
gcc/common/config/i386/i386-isas.h | 2 +
gcc/config.gcc | 3 +-
gcc/config/i386/avx10vpmldsabflydqintrin.h | 93 ++++++++
gcc/config/i386/cpuid.h | 1 +
gcc/config/i386/i386-builtin-types.def | 4 +
gcc/config/i386/i386-builtin.def | 5 +
gcc/config/i386/i386-c.cc | 2 +
gcc/config/i386/i386-expand.cc | 2 +
gcc/config/i386/i386-isa.def | 1 +
gcc/config/i386/i386-options.cc | 4 +-
gcc/config/i386/i386.opt | 5 +
gcc/config/i386/i386.opt.urls | 3 +
gcc/config/i386/immintrin.h | 2 +
gcc/config/i386/sse.md | 16 ++
gcc/doc/extend.texi | 5 +
gcc/doc/invoke.texi | 8 +-
gcc/doc/sourcebuild.texi | 3 +
gcc/testsuite/g++.dg/other/i386-2.C | 2 +-
gcc/testsuite/g++.dg/other/i386-3.C | 2 +-
gcc/testsuite/gcc.target/i386/avx-1.c | 7 +-
gcc/testsuite/gcc.target/i386/avx10-check.h | 3 +
.../gcc.target/i386/avx10vpmldsabflydq-1.c | 19 ++
.../gcc.target/i386/avx10vpmldsabflydq-2.c | 54 +++++
.../gcc.target/i386/avx10vpmldsabflydq-2.h | 198 ++++++++++++++++++
gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 +
gcc/testsuite/gcc.target/i386/sse-12.c | 2 +-
gcc/testsuite/gcc.target/i386/sse-13.c | 7 +-
gcc/testsuite/gcc.target/i386/sse-14.c | 7 +-
gcc/testsuite/gcc.target/i386/sse-22.c | 9 +-
gcc/testsuite/gcc.target/i386/sse-23.c | 7 +-
gcc/testsuite/lib/target-supports.exp | 17 ++
34 files changed, 510 insertions(+), 13 deletions(-)
create mode 100644 gcc/config/i386/avx10vpmldsabflydqintrin.h
create mode 100644 gcc/testsuite/gcc.target/i386/avx10vpmldsabflydq-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10vpmldsabflydq-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10vpmldsabflydq-2.h
diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index 0622f64ef31..3346d191cf3 100644
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -1076,6 +1076,8 @@ get_available_features (struct __processor_model
*cpu_model,
if (ace_usable)
if (ecx & bit_ACE)
ace_set = 1;
+ if (ecx & bit_AVX10VPMLDSABFLYDQ)
+ set_feature (FEATURE_AVX10VPMLDSABFLYDQ);
}
if (amx_usable)
{
diff --git a/gcc/common/config/i386/i386-common.cc
b/gcc/common/config/i386/i386-common.cc
index c28535a341f..a0bab45900b 100644
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -160,6 +160,8 @@ along with GCC; see the file COPYING3. If not see
(OPTION_MASK_ISA2_ACEV1_SET | OPTION_MASK_ISA2_ACEOPFP32)
#define OPTION_MASK_ISA2_ACEOPFP64_SET \
(OPTION_MASK_ISA2_ACEV1_SET | OPTION_MASK_ISA2_ACEOPFP64)
+#define OPTION_MASK_ISA2_AVX10VPMLDSABFLYDQ_SET \
+ (OPTION_MASK_ISA2_AVX10_1_SET | OPTION_MASK_ISA2_AVX10VPMLDSABFLYDQ)
/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
as -msse4.2. */
@@ -349,7 +351,8 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_AVX10_1_UNSET \
(OPTION_MASK_ISA2_AVX10_1 | OPTION_MASK_ISA2_AVX10_2_UNSET \
| OPTION_MASK_ISA2_AVX10V2AUX_UNSET | OPTION_MASK_ISA2_AVX10V1AUX_UNSET \
- | OPTION_MASK_ISA2_AVX10BMM_UNSET)
+ | OPTION_MASK_ISA2_AVX10BMM_UNSET \
+ | OPTION_MASK_ISA2_AVX10VPMLDSABFLYDQ_UNSET)
#define OPTION_MASK_ISA2_AVX10_2_UNSET \
(OPTION_MASK_ISA2_AVX10_2 | OPTION_MASK_ISA2_AVX10_3_UNSET)
#define OPTION_MASK_ISA2_AMX_AVX512_UNSET OPTION_MASK_ISA2_AMX_AVX512
@@ -374,6 +377,8 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_ACEOPFP16_UNSET OPTION_MASK_ISA2_ACEOPFP16
#define OPTION_MASK_ISA2_ACEOPFP32_UNSET OPTION_MASK_ISA2_ACEOPFP32
#define OPTION_MASK_ISA2_ACEOPFP64_UNSET OPTION_MASK_ISA2_ACEOPFP64
+#define OPTION_MASK_ISA2_AVX10VPMLDSABFLYDQ_UNSET \
+ OPTION_MASK_ISA2_AVX10VPMLDSABFLYDQ
/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
as -mno-sse4.1. */
@@ -1651,6 +1656,24 @@ ix86_handle_option (struct gcc_options *opts,
}
return true;
+ case OPT_mavx10vpmldsabflydq:
+ if (value)
+ {
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10VPMLDSABFLYDQ_SET;
+ opts->x_ix86_isa_flags2_explicit |=
+ OPTION_MASK_ISA2_AVX10VPMLDSABFLYDQ_SET;
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET;
+ opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET;
+ }
+ else
+ {
+ opts->x_ix86_isa_flags2 &=
+ ~OPTION_MASK_ISA2_AVX10VPMLDSABFLYDQ_UNSET;
+ opts->x_ix86_isa_flags2_explicit |=
+ OPTION_MASK_ISA2_AVX10VPMLDSABFLYDQ_UNSET;
+ }
+ return true;
+
case OPT_mfma:
if (value)
{
diff --git a/gcc/common/config/i386/i386-cpuinfo.h
b/gcc/common/config/i386/i386-cpuinfo.h
index 4e36284242a..79815bd7e51 100644
--- a/gcc/common/config/i386/i386-cpuinfo.h
+++ b/gcc/common/config/i386/i386-cpuinfo.h
@@ -294,6 +294,7 @@ enum processor_features
FEATURE_ACEOPFP16,
FEATURE_ACEOPFP32,
FEATURE_ACEOPFP64,
+ FEATURE_AVX10VPMLDSABFLYDQ,
CPU_FEATURE_MAX
};
diff --git a/gcc/common/config/i386/i386-isas.h
b/gcc/common/config/i386/i386-isas.h
index c3b8e9ee649..127f81d4223 100644
--- a/gcc/common/config/i386/i386-isas.h
+++ b/gcc/common/config/i386/i386-isas.h
@@ -202,4 +202,6 @@ ISA_NAMES_TABLE_START
ISA_NAMES_TABLE_ENTRY("aceopfp16", FEATURE_ACEOPFP16, P_NONE, "-maceopfp16")
ISA_NAMES_TABLE_ENTRY("aceopfp32", FEATURE_ACEOPFP32, P_NONE, "-maceopfp32")
ISA_NAMES_TABLE_ENTRY("aceopfp64", FEATURE_ACEOPFP64, P_NONE, "-maceopfp64")
+ ISA_NAMES_TABLE_ENTRY("avx10vpmldsabflydq", FEATURE_AVX10VPMLDSABFLYDQ,
+ P_NONE, "-mavx10vpmldsabflydq")
ISA_NAMES_TABLE_END
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 5b5559e7ac9..1466a37c50e 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -492,7 +492,8 @@ i[34567]86-*-* | x86_64-*-*)
avx10v2auxintrin.h avx10v1auxintrin.h acev1intrin.h
avx10_3int4fp4intrin.h avx10_3cvtbf16intrin.h
avx10_3vpinterleaveintrin.h acev2intrin.h
- aceopfp16intrin.h aceopfp32intrin.h aceopfp64intrin.h"
+ aceopfp16intrin.h aceopfp32intrin.h aceopfp64intrin.h
+ avx10vpmldsabflydqintrin.h"
;;
ia64-*-*)
extra_headers=ia64intrin.h
diff --git a/gcc/config/i386/avx10vpmldsabflydqintrin.h
b/gcc/config/i386/avx10vpmldsabflydqintrin.h
new file mode 100644
index 00000000000..d063df3c5c7
--- /dev/null
+++ b/gcc/config/i386/avx10vpmldsabflydqintrin.h
@@ -0,0 +1,93 @@
+/* Copyright (C) 2026 Free Software Foundation, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#if !defined _IMMINTRIN_H_INCLUDED
+#error "Never use <avx10vpmldsabflydqintrin.h> directly; include <immintrin.h>
instead."
+#endif
+
+#ifndef _AVX10VPMLDSABFLYDQINTRIN_H_INCLUDED
+#define _AVX10VPMLDSABFLYDQINTRIN_H_INCLUDED
+
+#if !defined(__AVX10VPMLDSABFLYDQ__)
+#pragma GCC push_options
+#pragma GCC target("avx10vpmldsabflydq")
+#define __DISABLE_AVX10VPMLDSABFLYDQ__
+#endif /* __AVX10VPMLDSABFLYDQ__ */
+
+#ifdef __OPTIMIZE__
+extern __inline __m128i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mldsabflydq_epi32 (__m128i __A, __m128i __B, __m128i __C, const int __M)
+{
+ return (__m128i) __builtin_ia32_mldsabflydq128 ((__v4si) __A,
+ (__v4si) __B,
+ (__v4si) __C,
+ __M);
+}
+
+extern __inline __m256i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mldsabflydq_epi32 (__m256i __A, __m256i __B, __m256i __C, const int __M)
+{
+ return (__m256i) __builtin_ia32_mldsabflydq256 ((__v8si) __A,
+ (__v8si) __B,
+ (__v8si) __C,
+ __M);
+}
+
+extern __inline __m512i
+__attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mldsabflydq_epi32 (__m512i __A, __m512i __B, __m512i __C, const int __M)
+{
+ return (__m512i) __builtin_ia32_mldsabflydq512 ((__v16si) __A,
+ (__v16si) __B,
+ (__v16si) __C,
+ __M);
+}
+
+#else
+#define _mm_mldsabflydq_epi32(A, B, C, M) \
+ (__m128i) __builtin_ia32_mldsabflydq128 ((__v4si)(__m128i)(A), \
+ (__v4si)(__m128i)(B), \
+ (__v4si)(__m128i)(C), \
+ (int)(M))
+
+#define _mm256_mldsabflydq_epi32(A, B, C, M) \
+ (__m256i) __builtin_ia32_mldsabflydq256 ((__v8si)(__m256i)(A), \
+ (__v8si)(__m256i)(B), \
+ (__v8si)(__m256i)(C), \
+ (int)(M))
+
+#define _mm512_mldsabflydq_epi32(A, B, C, M) \
+ (__m512i) __builtin_ia32_mldsabflydq512 ((__v16si)(__m512i)(A), \
+ (__v16si)(__m512i)(B), \
+ (__v16si)(__m512i)(C), \
+ (int)(M))
+#endif
+
+#ifdef __DISABLE_AVX10VPMLDSABFLYDQ__
+#undef __DISABLE_AVX10VPMLDSABFLYDQ__
+#pragma GCC pop_options
+#endif /* __DISABLE_AVX10VPMLDSABFLYDQ__ */
+
+#endif /* __AVX10VPMLDSABFLYDQINTRIN_H_INCLUDED */
diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h
index a73d4ba4395..81547b4bc71 100644
--- a/gcc/config/i386/cpuid.h
+++ b/gcc/config/i386/cpuid.h
@@ -146,6 +146,7 @@
#define bit_MOVRS (1 << 31)
/* %ecx */
+#define bit_AVX10VPMLDSABFLYDQ (1 << 7)
#define bit_ACE (1 << 11)
/* %edx */
diff --git a/gcc/config/i386/i386-builtin-types.def
b/gcc/config/i386/i386-builtin-types.def
index a923df99000..ea03eaa1f73 100644
--- a/gcc/config/i386/i386-builtin-types.def
+++ b/gcc/config/i386/i386-builtin-types.def
@@ -1553,3 +1553,7 @@ DEF_FUNCTION_TYPE (VOID, UQI, V16SF, V16SF, INT)
# ACEOPFP64 builtins
DEF_FUNCTION_TYPE (VOID, UQI, V8DF, V8DF, V8DF, INT)
+
+# AVX10VPMLDSABFLYDQ builtins
+DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, V8SI, INT)
+DEF_FUNCTION_TYPE (V16SI, V16SI, V16SI, V16SI, INT)
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 7e58284c4bc..802ebf30a0d 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -3545,6 +3545,11 @@ BDESC (0, OPTION_MASK_ISA2_AVX10_3,
CODE_FOR_vec_interleave_highv32hi_mask, "__b
BDESC (0, OPTION_MASK_ISA2_AVX10_3,
CODE_FOR_avx10_3_vec_interleave_lowv16hi_mask,
"__builtin_ia32_vpinterleavelw256_mask", IX86_BUILTIN_VPINTERLEAVELW256_MASK,
UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI)
BDESC (0, OPTION_MASK_ISA2_AVX10_3, CODE_FOR_vec_interleave_lowv32hi_mask,
"__builtin_ia32_vpinterleavelw512_mask", IX86_BUILTIN_VPINTERLEAVELW512_MASK,
UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI)
+/* AVX10VPMLDSABFLYDQ. */
+BDESC (0, OPTION_MASK_ISA2_AVX10VPMLDSABFLYDQ,
CODE_FOR_avx10_vpmldsabflydqv4si, "__builtin_ia32_mldsabflydq128",
IX86_BUILTIN_MLDSABFLYDQV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10VPMLDSABFLYDQ,
CODE_FOR_avx10_vpmldsabflydqv8si, "__builtin_ia32_mldsabflydq256",
IX86_BUILTIN_MLDSABFLYDQV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT)
+BDESC (0, OPTION_MASK_ISA2_AVX10VPMLDSABFLYDQ,
CODE_FOR_avx10_vpmldsabflydqv16si, "__builtin_ia32_mldsabflydq512",
IX86_BUILTIN_MLDSABFLYDQV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT)
+
/* Builtins with rounding support. */
BDESC_END (ARGS, ROUND_ARGS)
diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc
index 7aa15c3cb71..15a5e67836b 100644
--- a/gcc/config/i386/i386-c.cc
+++ b/gcc/config/i386/i386-c.cc
@@ -808,6 +808,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__ACEOPFP32__");
if (isa_flag2 & OPTION_MASK_ISA2_ACEOPFP64)
def_or_undef (parse_in, "__ACEOPFP64__");
+ if (isa_flag2 & OPTION_MASK_ISA2_AVX10VPMLDSABFLYDQ)
+ def_or_undef (parse_in, "__AVX10VPMLDSABFLYDQ__");
if (TARGET_IAMCU)
{
def_or_undef (parse_in, "__iamcu");
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index 02c03905906..830b8dc35e8 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -13324,6 +13324,8 @@ ix86_expand_args_builtin (const struct
builtin_description *d,
case V8SF_FTYPE_V8SF_V8SF_V8SI_INT:
case V16SF_FTYPE_V16SF_V16SF_V16SI_INT:
case V4SI_FTYPE_V4SI_V4SI_V4SI_INT:
+ case V8SI_FTYPE_V8SI_V8SI_V8SI_INT:
+ case V16SI_FTYPE_V16SI_V16SI_V16SI_INT:
nargs = 4;
nargs_constant = 1;
break;
diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def
index 705cb3c9a3d..6bb9adca48f 100644
--- a/gcc/config/i386/i386-isa.def
+++ b/gcc/config/i386/i386-isa.def
@@ -134,3 +134,4 @@ DEF_PTA(ACEV2)
DEF_PTA(ACEOPFP16)
DEF_PTA(ACEOPFP32)
DEF_PTA(ACEOPFP64)
+DEF_PTA(AVX10VPMLDSABFLYDQ)
diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index d736a85c887..7b5d9f416f6 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -283,7 +283,8 @@ static struct ix86_target_opts isa2_opts[] =
{ "-macev2", OPTION_MASK_ISA2_ACEV2 },
{ "-maceopfp16", OPTION_MASK_ISA2_ACEOPFP16 },
{ "-maceopfp32", OPTION_MASK_ISA2_ACEOPFP32 },
- { "-maceopfp64", OPTION_MASK_ISA2_ACEOPFP64 }
+ { "-maceopfp64", OPTION_MASK_ISA2_ACEOPFP64 },
+ { "-mavx10vpmldsabflydq", OPTION_MASK_ISA2_AVX10VPMLDSABFLYDQ }
};
static struct ix86_target_opts isa_opts[] =
{
@@ -1157,6 +1158,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree
args, char *p_strings[],
IX86_ATTR_ISA ("aceopfp16", OPT_maceopfp16),
IX86_ATTR_ISA ("aceopfp32", OPT_maceopfp32),
IX86_ATTR_ISA ("aceopfp64", OPT_maceopfp64),
+ IX86_ATTR_ISA ("avx10vpmldsabflydq", OPT_mavx10vpmldsabflydq),
/* enum options */
IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_),
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index bb4dd8d0b07..43bdc99686f 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -1437,3 +1437,8 @@ maceopfp64
Target Mask(ISA2_ACEOPFP64) Var(ix86_isa_flags2) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
AVX10.1, ACEv1 and ACEOPFP64 built-in functions and code generation.
+
+mavx10vpmldsabflydq
+Target Mask(ISA2_AVX10VPMLDSABFLYDQ) Var(ix86_isa_flags2) Save
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
+AVX10.1 and AVX10VPMLDSABFLYDQ built-in functions and code generation.
diff --git a/gcc/config/i386/i386.opt.urls b/gcc/config/i386/i386.opt.urls
index 96c8f1de0f2..57497e4039d 100644
--- a/gcc/config/i386/i386.opt.urls
+++ b/gcc/config/i386/i386.opt.urls
@@ -662,3 +662,6 @@ UrlSuffix(gcc/x86-Options.html#index-maceopfp32)
maceopfp64
UrlSuffix(gcc/x86-Options.html#index-maceopfp64)
+mavx10vpmldsabflydq
+UrlSuffix(gcc/x86-Options.html#index-mavx10vpmldsabflydq)
+
diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h
index 1a7eecffba2..0933a03a550 100644
--- a/gcc/config/i386/immintrin.h
+++ b/gcc/config/i386/immintrin.h
@@ -182,4 +182,6 @@
#include <aceopfp64intrin.h>
+#include <avx10vpmldsabflydqintrin.h>
+
#endif /* _IMMINTRIN_H_INCLUDED */
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index b50981da6aa..aa4382a3cbc 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -323,6 +323,9 @@
UNSPEC_VCVTBF162UF8S
UNSPEC_VCVTHF82BF16
UNSPEC_VCVTBF82BF16
+
+ ;; For AVX10VPMLDSABFLYDQ suppport
+ UNSPEC_VPMLDSABFLYDQ
])
(define_c_enum "unspecv" [
@@ -35534,3 +35537,16 @@
"TARGET_ACEOPFP64"
"top1pd\t{<round_op3>%2, %g1, %%tmm%c0|tmm%c0, %g1, %2<round_op3>}"
[(set_attr "prefix" "evex")])
+
+(define_insn "avx10_vpmldsabflydq<mode>"
+ [(set (match_operand:VI4_AVX512F 0 "register_operand" "=v")
+ (unspec:VI4_AVX512F
+ [(match_operand:VI4_AVX512F 1 "register_operand" "0")
+ (match_operand:VI4_AVX512F 2 "register_operand" "v")
+ (match_operand:VI4_AVX512F 3 "register_operand" "v")
+ (match_operand:SI 4 "const_0_to_255_operand" "n")]
+ UNSPEC_VPMLDSABFLYDQ))]
+ "TARGET_AVX10VPMLDSABFLYDQ"
+ "vpmldsabflydq\t{%4, %3, %2, %0|%0, %2, %3, %4}"
+ [(set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 1c37b8a3bbb..b7dfea3a14c 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -9610,6 +9610,11 @@ Enable/disable the generation of the ACEOPFP32
instructions.
@itemx no-aceopfp64
Enable/disable the generation of the ACEOPFP64 instructions.
+@cindex @code{target("avx10vpmldsabflydq")}, x86
+@item avx10vpmldsabflydq
+@itemx no-avx10vpmldsabflydq
+Enable/disable the generation of the AVX10VPMLDSABFLYDQ instructions.
+
@atindex @code{target("cld")}, x86
@item cld
@itemx no-cld
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index cbce8d0f91b..cc2a62b7304 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1556,7 +1556,7 @@ See RS/6000 and PowerPC Options.
-mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf
-musermsr -mavx10.1 -mavx10.2 -mamx-avx512 -mmovrs -mamx-movrs
-mavx512bmm -mavx10v2aux -macev1 -mavx10v1aux -mavx10.3 -mavx10bmm
--macev2 -maceopfp16 -maceopfp32 -maceopfp64
+-macev2 -maceopfp16 -maceopfp32 -maceopfp64 -mavx10vpmldsabflydq
-mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops
-minline-stringops-dynamically -mstringop-strategy=@var{alg}
-mkl -mwidekl
@@ -36470,6 +36470,12 @@ AVX10.1, ACEv1 and ACEOPFP32 built-in functions and
code generation.
@item -maceopfp64
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
AVX10.1, ACEv1 and ACEOPFP64 built-in functions and code generation.
+
+@opindex mavx10vpmldsabflydq
+@opindex mno-avx10vpmldsabflydq
+@item -mavx10vpmldsabflydq
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
+AVX10.1 and AVX10VPMLDSABFLYDQ built-in functions and code generation.
@end table
These additional options are available for the x86 processor family.
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 1dbdd3c88bf..b9e26d0c77d 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2737,6 +2737,9 @@ Target supports the execution of @code{avx10v1aux}
instructions.
@item avx10v2aux
Target supports the execution of @code{avx10v2aux} instructions.
+@item avx10vpmldsabflydq
+Target supports the execution of @code{avx10vpmldsabflydq} instructions.
+
@item avx2
Target supports compiling @code{avx2} instructions.
diff --git a/gcc/testsuite/g++.dg/other/i386-2.C
b/gcc/testsuite/g++.dg/other/i386-2.C
index 7a5ab46a6a5..35e7f0340a7 100644
--- a/gcc/testsuite/g++.dg/other/i386-2.C
+++ b/gcc/testsuite/g++.dg/other/i386-2.C
@@ -1,5 +1,5 @@
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2
-mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp
-mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt
-msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx
-mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize
-mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma
-mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint
-mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2 -mamx-avx512
-mamx-fp8 -mmovrs -mamx-movrs -mavx10v2aux -macev1 -mavx10.3 -macev2
-maceopfp16 -maceopfp32 -maceopfp64" } */
+/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2
-mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp
-mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt
-msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku -msgx
-mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect -mserialize
-mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma
-mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint
-mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2 -mamx-avx512
-mamx-fp8 -mmovrs -mamx-movrs -mavx10v2aux -macev1 -mavx10.3 -macev2
-maceopfp16 -maceopfp32 -maceopfp64 -mavx10vpmldsabflydq" } */
/* { dg-skip-if "requires hosted libstdc++ for cstdlib malloc" { ! hostedlib }
} */
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
diff --git a/gcc/testsuite/g++.dg/other/i386-3.C
b/gcc/testsuite/g++.dg/other/i386-3.C
index f5d34e8999d..1a3b92379d5 100644
--- a/gcc/testsuite/g++.dg/other/i386-3.C
+++ b/gcc/testsuite/g++.dg/other/i386-3.C
@@ -1,5 +1,5 @@
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx
-mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm
-mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr
-mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku
-msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect
-mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni
-mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi
-mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2
-mamx-avx512 -mamx-fp8 -mmovrs -mamx-movrs -mavx10v2aux -macev1 -mavx10.3
-macev2 -maceopfp16 -maceopfp32 -maceopfp64" } */
+/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx
-mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm
-mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr
-mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku
-msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect
-mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni
-mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi
-mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2
-mamx-avx512 -mamx-fp8 -mmovrs -mamx-movrs -mavx10v2aux -macev1 -mavx10.3
-macev2 -maceopfp16 -maceopfp32 -maceopfp64 -mavx10vpmldsabflydq" } */
/* { dg-skip-if "requires hosted libstdc++ for cstdlib malloc" { ! hostedlib }
} */
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
diff --git a/gcc/testsuite/gcc.target/i386/avx-1.c
b/gcc/testsuite/gcc.target/i386/avx-1.c
index 0d26fad7bc4..8f0ce9e2248 100644
--- a/gcc/testsuite/gcc.target/i386/avx-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow
-mavx -mavx2 -maes -mpclmul -mgfni -mprefetchi -mavx10.2 -mmovrs -mavx10v2aux
-macev1 -mavx10.3 -macev2 -maceopfp16 -maceopfp32 -maceopfp64" } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow
-mavx -mavx2 -maes -mpclmul -mgfni -mprefetchi -mavx10.2 -mmovrs -mavx10v2aux
-macev1 -mavx10.3 -macev2 -maceopfp16 -maceopfp32 -maceopfp64
-mavx10vpmldsabflydq" } */
/* { dg-add-options bind_pic_locally } */
#include <mm_malloc.h>
@@ -968,6 +968,11 @@
#define __builtin_ia32_top1pd_round(W, A, B, C, D) __builtin_ia32_top1pd_round
(1, A, B, C, 4)
#endif
+/* avx10vpmldsabflydqintrin.h */
+#define __builtin_ia32_mldsabflydq128(A, B, C, M)
__builtin_ia32_mldsabflydq128 (A, B, C, 1)
+#define __builtin_ia32_mldsabflydq256(A, B, C, M)
__builtin_ia32_mldsabflydq256 (A, B, C, 1)
+#define __builtin_ia32_mldsabflydq512(A, B, C, M)
__builtin_ia32_mldsabflydq512 (A, B, C, 1)
+
#include <wmmintrin.h>
#include <immintrin.h>
#include <mm3dnow.h>
diff --git a/gcc/testsuite/gcc.target/i386/avx10-check.h
b/gcc/testsuite/gcc.target/i386/avx10-check.h
index bad43b9b38e..34a19e067c8 100644
--- a/gcc/testsuite/gcc.target/i386/avx10-check.h
+++ b/gcc/testsuite/gcc.target/i386/avx10-check.h
@@ -42,6 +42,9 @@ main ()
#endif
#ifdef AVX10_3
&& __builtin_cpu_supports ("avx10.3")
+#endif
+#ifdef AVX10VPMLDSABFLYDQ
+ && __builtin_cpu_supports ("avx10vpmldsabflydq")
#endif
&& avx10_os_support ())
{
diff --git a/gcc/testsuite/gcc.target/i386/avx10vpmldsabflydq-1.c
b/gcc/testsuite/gcc.target/i386/avx10vpmldsabflydq-1.c
new file mode 100644
index 00000000000..3026074104f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10vpmldsabflydq-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64-v3 -mavx10vpmldsabflydq -O2" } */
+/* { dg-final { scan-assembler-times "vpmldsabflydq\[
\\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpmldsabflydq\[
\\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpmldsabflydq\[
\\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[
\\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m128i x1, x2, x3;
+volatile __m256i y, y2, y3;
+volatile __m512i z1, z2, z3;
+
+void extern
+avx10vpmldsabflydq_test (void)
+{
+ x1 = _mm_mldsabflydq_epi32 (x1, x2, x3, 1);
+ y = _mm256_mldsabflydq_epi32 (y, y2, y3, 1);
+ z1 = _mm512_mldsabflydq_epi32 (z1, z2, z3, 1);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10vpmldsabflydq-2.c
b/gcc/testsuite/gcc.target/i386/avx10vpmldsabflydq-2.c
new file mode 100644
index 00000000000..520babcdb3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10vpmldsabflydq-2.c
@@ -0,0 +1,54 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -march=x86-64-v3 -mavx10vpmldsabflydq" } */
+/* { dg-require-effective-target avx10vpmldsabflydq } */
+
+#define AVX10VPMLDSABFLYQ
+#define AVX10
+#include <stdlib.h>
+
+#define Q 8380417
+#define QINV 58728449
+
+static int
+montmulq (int a, int b)
+{
+ long long t1, t2, t3, c;
+ t1 = (long long) a * (long long) b;
+ t2 = (t1 & 0xffffffff) * QINV;
+ t3 = (t2 & 0xffffffff) * Q;
+ c = (t1 - t3) >> 32;
+ return (int) c;
+}
+
+static void
+ctbfly (int a, int b, int z, int* a1, int* b1)
+{
+ int m = montmulq (b, z);
+ *a1 = a + m;
+ *b1 = a - m;
+}
+
+static void
+gsbfly (int a, int b, int z, int *a1, int* b1)
+{
+ int m = montmulq (a - b, z);
+ *a1 = a + b;
+ *b1 = m;
+}
+
+#include "avx10vpmldsabflydq-2.h"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx10vpmldsabflydq-2.h"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx10vpmldsabflydq-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx10vpmldsabflydq-2.h
b/gcc/testsuite/gcc.target/i386/avx10vpmldsabflydq-2.h
new file mode 100644
index 00000000000..0de1901a6b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10vpmldsabflydq-2.h
@@ -0,0 +1,198 @@
+#include "avx10-helper.h"
+#include <immintrin.h>
+
+#define SIZE (AVX512F_LEN / 32)
+
+static void
+CALC (int *res, int *src1, int *src2, int *src3, int imm)
+{
+ int j;
+ int i0, i1, i2;
+
+ i0 = imm & 0x03;
+ i1 = (imm & 0x0c) >> 2;
+ i2 = (imm & 0x10) >> 4;
+
+ for (j = 0; j < SIZE / 2; j++)
+ {
+ int a, b, z, a1, b1, resa_high, resb_high;
+ unsigned resa_low, resb_low;
+
+ if (i1 == 0)
+ {
+ a = src1[j * 2] & 0x1ffffff;
+ b = src2[j * 2] & 0x1ffffff;
+ }
+ else if (i1 == 1)
+ {
+ a = src1[j * 2 + 1] & 0x1ffffff;
+ b = src2[j * 2 + 1] & 0x1ffffff;
+ }
+ else if (i1 == 2)
+ {
+ a = src2[j * 2 - j % 2] & 0x1ffffff;
+ b = src2[j * 2 - j % 2 + 2] & 0x1ffffff;
+ }
+ else
+ {
+ a = src2[j * 2] & 0x1ffffff;
+ b = src2[j * 2 + 1] & 0x1ffffff;
+ }
+
+ if (i0 == 1)
+ z = src3[j / 2 * 4 + 2] & 0x1ffffff;
+ else if (i0 == 2)
+ z = src3[j * 2] & 0x1ffffff;
+ else
+ z = src3[j / 2 * 4] & 0x1ffffff;
+
+ if (i2 == 0)
+ ctbfly (a, b, z, &a1, &b1);
+ else
+ gsbfly (a, b, z, &a1, &b1);
+
+ resa_low = a1 & 0x7fffff;
+ resa_high = a1 >> 23;
+ resb_low = b1 & 0x7fffff;
+ resb_high = b1 >> 23;
+
+ res[j * 2] = resa_low + (resa_high << 13) - resa_high;
+ res[j * 2 + 1] = resb_low + (resb_high << 13) - resb_high;
+
+ }
+}
+
+static void
+TEST (void)
+{
+ UNION_TYPE (AVX512F_LEN, i_d) src1, src2, src3, res;
+ int res_ref[SIZE];
+ int i, j;
+
+ for (i = 0; i < SIZE; i++)
+ {
+ src1.a[i] = i;
+ src2.a[i] = (i << 10) + (i % 3) ;
+ src3.a[i] = (i << 20) + ((i % 5) << 10) + (i % 7);
+ }
+
+ CALC (res_ref, src1.a, src2.a, src3.a, 0);
+ res.x = INTRINSIC (_mldsabflydq_epi32) (src1.x, src2.x, src3.x, 0);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+ abort ();
+
+ CALC (res_ref, src1.a, src2.a, src3.a, 1);
+ res.x = INTRINSIC (_mldsabflydq_epi32) (src1.x, src2.x, src3.x, 1);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+ abort ();
+
+ CALC (res_ref, src1.a, src2.a, src3.a, 2);
+ res.x = INTRINSIC (_mldsabflydq_epi32) (src1.x, src2.x, src3.x, 2);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+ abort ();
+
+ CALC (res_ref, src1.a, src2.a, src3.a, 4);
+ res.x = INTRINSIC (_mldsabflydq_epi32) (src1.x, src2.x, src3.x, 4);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+ abort ();
+
+ CALC (res_ref, src1.a, src2.a, src3.a, 5);
+ res.x = INTRINSIC (_mldsabflydq_epi32) (src1.x, src2.x, src3.x, 5);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+ abort ();
+
+ CALC (res_ref, src1.a, src2.a, src3.a, 6);
+ res.x = INTRINSIC (_mldsabflydq_epi32) (src1.x, src2.x, src3.x, 6);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+ abort ();
+
+ CALC (res_ref, src1.a, src2.a, src3.a, 8);
+ res.x = INTRINSIC (_mldsabflydq_epi32) (src1.x, src2.x, src3.x, 8);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+ abort ();
+
+ CALC (res_ref, src1.a, src2.a, src3.a, 9);
+ res.x = INTRINSIC (_mldsabflydq_epi32) (src1.x, src2.x, src3.x, 9);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+ abort ();
+
+ CALC (res_ref, src1.a, src2.a, src3.a, 10);
+ res.x = INTRINSIC (_mldsabflydq_epi32) (src1.x, src2.x, src3.x, 10);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+ abort ();
+
+ CALC (res_ref, src1.a, src2.a, src3.a, 12);
+ res.x = INTRINSIC (_mldsabflydq_epi32) (src1.x, src2.x, src3.x, 12);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+ abort ();
+
+ CALC (res_ref, src1.a, src2.a, src3.a, 13);
+ res.x = INTRINSIC (_mldsabflydq_epi32) (src1.x, src2.x, src3.x, 13);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+ abort ();
+
+ CALC (res_ref, src1.a, src2.a, src3.a, 14);
+ res.x = INTRINSIC (_mldsabflydq_epi32) (src1.x, src2.x, src3.x, 14);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+ abort ();
+
+ CALC (res_ref, src1.a, src2.a, src3.a, 16);
+ res.x = INTRINSIC (_mldsabflydq_epi32) (src1.x, src2.x, src3.x, 16);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+ abort ();
+
+ CALC (res_ref, src1.a, src2.a, src3.a, 17);
+ res.x = INTRINSIC (_mldsabflydq_epi32) (src1.x, src2.x, src3.x, 17);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+ abort ();
+
+ CALC (res_ref, src1.a, src2.a, src3.a, 18);
+ res.x = INTRINSIC (_mldsabflydq_epi32) (src1.x, src2.x, src3.x, 18);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+ abort ();
+
+ CALC (res_ref, src1.a, src2.a, src3.a, 20);
+ res.x = INTRINSIC (_mldsabflydq_epi32) (src1.x, src2.x, src3.x, 20);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+ abort ();
+
+ CALC (res_ref, src1.a, src2.a, src3.a, 21);
+ res.x = INTRINSIC (_mldsabflydq_epi32) (src1.x, src2.x, src3.x, 21);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+ abort ();
+
+ CALC (res_ref, src1.a, src2.a, src3.a, 22);
+ res.x = INTRINSIC (_mldsabflydq_epi32) (src1.x, src2.x, src3.x, 22);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+ abort ();
+
+ CALC (res_ref, src1.a, src2.a, src3.a, 24);
+ res.x = INTRINSIC (_mldsabflydq_epi32) (src1.x, src2.x, src3.x, 24);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+ abort ();
+
+ CALC (res_ref, src1.a, src2.a, src3.a, 25);
+ res.x = INTRINSIC (_mldsabflydq_epi32) (src1.x, src2.x, src3.x, 25);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+ abort ();
+
+ CALC (res_ref, src1.a, src2.a, src3.a, 26);
+ res.x = INTRINSIC (_mldsabflydq_epi32) (src1.x, src2.x, src3.x, 26);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+ abort ();
+
+ CALC (res_ref, src1.a, src2.a, src3.a, 28);
+ res.x = INTRINSIC (_mldsabflydq_epi32) (src1.x, src2.x, src3.x, 28);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+ abort ();
+
+ CALC (res_ref, src1.a, src2.a, src3.a, 29);
+ res.x = INTRINSIC (_mldsabflydq_epi32) (src1.x, src2.x, src3.x, 29);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+ abort ();
+
+ CALC (res_ref, src1.a, src2.a, src3.a, 30);
+ res.x = INTRINSIC (_mldsabflydq_epi32) (src1.x, src2.x, src3.x, 30);
+ if (UNION_CHECK (AVX512F_LEN, i_d) (res, res_ref))
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
index f734b9a6d2a..4f4fde0ed66 100644
--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
@@ -101,6 +101,7 @@ extern void test_acev2 (void)
__attribute__((__target__("acev2")));
extern void test_aceopfp16 (void)
__attribute__((__target__("aceopfp16")));
extern void test_aceopfp32 (void)
__attribute__((__target__("aceopfp32")));
extern void test_aceopfp64 (void)
__attribute__((__target__("aceopfp64")));
+extern void test_avx10vpmldsabflydq (void)
__attribute__((__target__("avx10vpmldsabflydq")));
extern void test_no_sgx (void)
__attribute__((__target__("no-sgx")));
extern void test_no_avx512vpopcntdq(void)
__attribute__((__target__("no-avx512vpopcntdq")));
@@ -203,6 +204,7 @@ extern void test_no_acev2 (void)
__attribute__((__target__("no-acev2")));
extern void test_no_aceopfp16 (void)
__attribute__((__target__("no-aceopfp16")));
extern void test_no_aceopfp32 (void)
__attribute__((__target__("no-aceopfp32")));
extern void test_no_aceopfp64 (void)
__attribute__((__target__("no-aceopfp64")));
+extern void test_no_avx10vpmldsabflydq (void)
__attribute__((__target__("no-avx10vpmldsabflydq")));
extern void test_arch_nocona (void)
__attribute__((__target__("arch=nocona")));
extern void test_arch_core2 (void)
__attribute__((__target__("arch=core2")));
diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c
b/gcc/testsuite/gcc.target/i386/sse-12.c
index c3c32a43b51..152783da99e 100644
--- a/gcc/testsuite/gcc.target/i386/sse-12.c
+++ b/gcc/testsuite/gcc.target/i386/sse-12.c
@@ -3,7 +3,7 @@
popcntintrin.h gfniintrin.h and mm_malloc.h are usable
with -O -std=c89 -pedantic-errors. */
/* { dg-do compile } */
-/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx
-mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm
-mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr
-mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku
-msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect
-mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni
-mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex
-mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2 -mamx-avx512 -mamx-fp8 -mmovrs
-mamx-movrs -mavx10v2aux -macev1 -mavx10.3 -macev2 -maceopfp16 -maceopfp32
-maceopfp64" } */
+/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx
-mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm
-mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr
-mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx -mclzero -mpku
-msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd -mavx512vp2intersect
-mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni
-mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex
-mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2 -mamx-avx512 -mamx-fp8 -mmovrs
-mamx-movrs -mavx10v2aux -macev1 -mavx10.3 -macev2 -maceopfp16 -maceopfp32
-maceopfp64 -mavx10vpmldsabflydq" } */
#include <x86intrin.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c
b/gcc/testsuite/gcc.target/i386/sse-13.c
index 4d9b7e15ce3..7bc8fa5c3c2 100644
--- a/gcc/testsuite/gcc.target/i386/sse-13.c
+++ b/gcc/testsuite/gcc.target/i386/sse-13.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a
-m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi
-mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw
-madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt
-mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni
-mpconfig -mwbnoinvd -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8
-mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert
-mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3
-msha512 -msm4 -mavx10.2 -mamx-avx512 -mamx-fp8 -mmovrs -mamx-movrs
-mavx10v2aux -macev1 -mavx10.3 -macev2 -maceopfp16 -maceopfp32 -maceopfp64" } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a
-m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi
-mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw
-madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt
-mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni
-mpconfig -mwbnoinvd -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8
-mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert
-mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3
-msha512 -msm4 -mavx10.2 -mamx-avx512 -mamx-fp8 -mmovrs -mamx-movrs
-mavx10v2aux -macev1 -mavx10.3 -macev2 -maceopfp16 -maceopfp32 -maceopfp64
-mavx10vpmldsabflydq" } */
/* { dg-add-options bind_pic_locally } */
#include <mm_malloc.h>
@@ -975,4 +975,9 @@
#define __builtin_ia32_top1pd_round(W, A, B, C, D) __builtin_ia32_top1pd_round
(1, A, B, C, 4)
#endif
+/* avx10vpmldsabflydqintrin.h */
+#define __builtin_ia32_mldsabflydq128(A, B, C, M)
__builtin_ia32_mldsabflydq128 (A, B, C, 1)
+#define __builtin_ia32_mldsabflydq256(A, B, C, M)
__builtin_ia32_mldsabflydq256 (A, B, C, 1)
+#define __builtin_ia32_mldsabflydq512(A, B, C, M)
__builtin_ia32_mldsabflydq512 (A, B, C, 1)
+
#include <x86intrin.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c
b/gcc/testsuite/gcc.target/i386/sse-14.c
index 8a35441d817..2cdba15b174 100644
--- a/gcc/testsuite/gcc.target/i386/sse-14.c
+++ b/gcc/testsuite/gcc.target/i386/sse-14.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a
-m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi
-mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw
-madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx
-mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd
-mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16
-mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16
-mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2
-mamx-avx512 -mamx-fp8 -mmovrs -mamx-movrs -mavx10v2aux -macev1 -mavx10.3
-macev2 -maceopfp16 -maceopfp32 -maceopfp64" } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a
-m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi
-mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw
-madx -mfxsr -mxsaveopt -msha -mxsavec -mxsaves -mclflushopt -mclwb -mmwaitx
-mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -menqcmd
-mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16
-mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16
-mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mavx10.2
-mamx-avx512 -mamx-fp8 -mmovrs -mamx-movrs -mavx10v2aux -macev1 -mavx10.3
-macev2 -maceopfp16 -maceopfp32 -maceopfp64 -mavx10vpmldsabflydq" } */
/* { dg-add-options bind_pic_locally } */
#include <mm_malloc.h>
@@ -1280,3 +1280,8 @@ test_2vxt (_tile_op1_round_ps, 1, __m512, __m512, 4)
test_3vt (_tile_op1pd, 1, __m512d, __m512d, __m512d)
test_3vxt (_tile_op1_round_pd, 1, __m512d, __m512d, __m512d, 4)
#endif
+
+/* avx10vpmldsabflydqintrin.h */
+test_3 (_mm_mldsabflydq_epi32, __m128i, __m128i, __m128i, __m128i, 1)
+test_3 (_mm256_mldsabflydq_epi32, __m256i, __m256i, __m256i, __m256i, 1)
+test_3 (_mm512_mldsabflydq_epi32, __m512i, __m512i, __m512i, __m512i, 1)
diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c
b/gcc/testsuite/gcc.target/i386/sse-22.c
index 9c554bd2436..f4238408988 100644
--- a/gcc/testsuite/gcc.target/i386/sse-22.c
+++ b/gcc/testsuite/gcc.target/i386/sse-22.c
@@ -128,7 +128,7 @@
#ifndef DIFFERENT_PRAGMAS
-#pragma GCC target
("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,gfni,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2,amx-avx512,amx-fp8,movrs,amx-movrs,avx10v2aux,acev1,avx10.3,acev2,aceopfp16,aceopfp32,aceopfp64")
+#pragma GCC target
("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,gfni,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2,amx-avx512,amx-fp8,movrs,amx-movrs,avx10v2aux,acev1,avx10.3,acev2,aceopfp16,aceopfp32,aceopfp64,avx10vpmldsabflydq")
#endif
/* Following intrinsics require immediate arguments. They
@@ -245,7 +245,7 @@ test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1)
/* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM/AVX512F/SHA) */
#ifdef DIFFERENT_PRAGMAS
-#pragma GCC target
("avx,avx2,rdrnd,fsgsbase,f16c,rtm,sha,gfni,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2,amx-avx512,amx-fp8,movrs,amx-movrs,avx10v2aux,acev1,avx10.3,acev2,aceopfp16,aceopfp32,aceopfp64")
+#pragma GCC target
("avx,avx2,rdrnd,fsgsbase,f16c,rtm,sha,gfni,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2,amx-avx512,amx-fp8,movrs,amx-movrs,avx10v2aux,acev1,avx10.3,acev2,aceopfp16,aceopfp32,aceopfp64,avx10vpmldsabflydq")
#endif
#include <immintrin.h>
test_1 (_cvtss_sh, unsigned short, float, 1)
@@ -1321,3 +1321,8 @@ test_2vxt (_tile_op1_round_ps, 1, __m512, __m512, 4)
test_3vt (_tile_op1pd, 1, __m512d, __m512d, __m512d)
test_3vxt (_tile_op1_round_pd, 1, __m512d, __m512d, __m512d, 4)
#endif
+
+/* avx10vpmldsabflydqintrin.h */
+test_3 (_mm_mldsabflydq_epi32, __m128i, __m128i, __m128i, __m128i, 1)
+test_3 (_mm256_mldsabflydq_epi32, __m256i, __m256i, __m256i, __m256i, 1)
+test_3 (_mm512_mldsabflydq_epi32, __m512i, __m512i, __m512i, __m512i, 1)
diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c
b/gcc/testsuite/gcc.target/i386/sse-23.c
index 9552dafc2e0..ea0d14c8b75 100644
--- a/gcc/testsuite/gcc.target/i386/sse-23.c
+++ b/gcc/testsuite/gcc.target/i386/sse-23.c
@@ -950,6 +950,11 @@
#define __builtin_ia32_top1pd_round(W, A, B, C, D) __builtin_ia32_top1pd_round
(1, A, B, C, 4)
#endif
-#pragma GCC target
("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,xsavec,xsaves,clflushopt,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,vpclmulqdq,pconfig,wbnoinvd,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2,amx-avx512,amx-fp8,movrs,amx-movrs,avx10v2aux,acev1,avx10.3,acev2,aceopfp16,aceopfp32,aceopfp64")
+/* avx10vpmldsabflydqintrin.h */
+#define __builtin_ia32_mldsabflydq128(A, B, C, M)
__builtin_ia32_mldsabflydq128 (A, B, C, 1)
+#define __builtin_ia32_mldsabflydq256(A, B, C, M)
__builtin_ia32_mldsabflydq256 (A, B, C, 1)
+#define __builtin_ia32_mldsabflydq512(A, B, C, M)
__builtin_ia32_mldsabflydq512 (A, B, C, 1)
+
+#pragma GCC target
("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,sha,xsavec,xsaves,clflushopt,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,vpclmulqdq,pconfig,wbnoinvd,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3,sha512,sm4,avx10.2,amx-avx512,amx-fp8,movrs,amx-movrs,avx10v2aux,acev1,avx10.3,acev2,aceopfp16,aceopfp32,aceopfp64,avx10vpmldsabflydq")
#include <x86intrin.h>
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 520b9300081..c01b32c8240 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -12166,6 +12166,23 @@ proc check_effective_target_aceopfp64 { } {
} "-maceopfp64" ]
}
+# Return 1 if avx10vpmldsabflydq instructions can be compiled.
+proc check_effective_target_avx10vpmldsabflydq { } {
+ return [check_no_compiler_messages avx10vpmldsabflydq object {
+ typedef int __m128i __attribute__ ((__vector_size__ (16)));
+ typedef int __v4si __attribute__ ((__vector_size__ (16)));
+ __m128i
+ _mm_mldsabflydq_epi32 (__m128i __A, __m128i __B,
+ __m128i __C)
+ {
+ return (__m128i) __builtin_ia32_mldsabflydq128 ((__v4si) __A,
+ (__v4si) __B,
+ (__v4si) __C,
+ 1);
+ }
+ } "-mavx10vpmldsabflydq" ]
+}
+
# Return 1 if sse instructions can be compiled.
proc check_effective_target_sse { } {
return [check_no_compiler_messages sse object {
--
2.31.1
