I have a processor which does not have hardware register interlocks, somewhat like the MIPS I. A register used in one instruction may not be referenced for a certain number of instructions.
If I recall correctly, for the MIPS I, the assembler handled inserting nop instructions when it found a register interlock. Are there any targets with register interlock where gcc handles moving instructions between conflicting instructions? Any suggestions on how this might be represented in .md files? It doesn't seem that the pipeline description would seem appropriate. -- Michael Eager [EMAIL PROTECTED] 1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
