Richard Sandiford wrote:
Michael Eager <[EMAIL PROTECTED]> writes:
I have a processor which does not have hardware
register interlocks, somewhat like the MIPS I.
A register used in one instruction may not be
referenced for a certain number of instructions.
If I recall correctly, for the MIPS I, the assembler
handled inserting nop instructions when it found a
register interlock.
Are there any targets with register interlock where
gcc handles moving instructions between conflicting
instructions?
FWIW, modern GCCs do do this for MIPS I. We wanted to allow GCC to
lay out functions itself, rather than relying so much on the assembler.
(Overly conservative length estimates can lead to unnecessary long-branch
sequences, among other things.) See mips_reorg for the code.
As well as the ia64 example Paul mentioned, you might want to look
at vr4130_align_insns, which is another subroutine of mips_reorg.
These days, you might be better off using the DF machinery.
The md_reorg code could look something like:
/* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. */
compute_bb_for_insn ();
/* Create def-use chains. */
df_chain_add_problem (DF_UD_CHAIN);
df_analyze ();
...your stuff here...
df_finish_pass (false);
free_bb_for_insn ();
You can then walk the DF_INSN_USES for each instruction and get a list
of their possible definitions.
Richard
Thanks Richard and Paul. Good pointers for me to follow.
--
Michael Eager [EMAIL PROTECTED]
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
