Hi all.
This is a question related with current development of Aarch64 backend.
In latest trunk revision of GCC 5.0, in directory gcc/config/arm there
are following files:
cortex-a{8,9,15,17}.md
cortex-a{8,9,15,17}-neon.md
These files contain constructions like
(define_insn_reservation insn-name default_latency condition regexp)
for both scalar and vector (NEON) instructions.
But for AdvSIMD aarch64 instructions in cortex-a53.md only the following
lines can be found:
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Crude Advanced SIMD approximation.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_insn_reservation "cortex_53_advsimd" 4
(and (eq_attr "tune" "cortexa53")
(eq_attr:q "is_neon_type" "yes"))
"cortex_a53_simd0")
Does it mean that all AdvSIMD instructions for cortex-a53 are supposed
to be of latency = 4?
In cortex-a57.md the description for "neon" instructions is more full,
it contains a lot of statements for different SIMD instructions.
It appeared in trunk just a month ago.
Are there any plans to release detailed pipeline descriptions for SIMD
instructions for cortex-a53?
How can it influence the performance of the generated code?
--
Best regards,
Ilya Palachev
