;; Crude Advanced SIMD approximation.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(define_insn_reservation "cortex_53_advsimd" 4
(and (eq_attr "tune" "cortexa53")
(eq_attr:q "is_neon_type" "yes"))
"cortex_a53_simd0")
Does it mean that all AdvSIMD instructions for cortex-a53 are supposed
to be of latency = 4?
Yes.
In cortex-a57.md the description for "neon" instructions is more full,
it contains a lot of statements for different SIMD instructions.
It appeared in trunk just a month ago.
Yes.
Are there any plans to release detailed pipeline descriptions for SIMD
instructions for cortex-a53?
> How can it influence the performance of the generated code?
No, we have no immediate plans. Obviously if we find a reason and
workloads where such changes are merited it will be picked up.
That being said I believe the current description isn't too bad on the
Cortex-A53 - it's definitely better than having none at all.
regards
Ramana
--
Best regards,
Ilya Palachev
