I've attached a simple counter testbench. I've compiled the current code
from svn and get the same issue. The only other tag listed in the VHDL
tag file that works is function. Is the correct set of tags been called?
Thanks,
Kelvin
Nick Treleaven wrote:
On Fri, 20 Nov 2009 11:45:16 +0000
Kelvin Gardiner <[email protected]> wrote:
What I meant by symbols was the symbols tab at the the right-hand side
of the window. When editing a C file this list functions, variables
etc. I'd like similar functionality for VHDL and Verilog.
If you provide a sample file I can try to improve the symbols parsed.
I think probably the problem is the tagmanager/vhdl.c parser hasn't
been updated to work with tagmanager tag types (VhdlKinds).
Regards,
Nick
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library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity counter_tb is
end counter_tb;
architecture counter_tb of counter_tb is
component counter
port ( count : out std_logic_vector(3 downto 0);
clk : in std_logic;
enable: in std_logic;
reset : in std_logic);
end component ;
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal enable : std_logic := '0';
signal count : std_logic_vector(3 downto 0);
begin
dut : counter
port map (
count => count,
clk => clk,
enable=> enable,
reset => reset );
clock : process
begin
wait for 1 ns; clk <= not clk;
end process clock;
stimulus : process
begin
wait for 5 ns; reset <= '1';
wait for 4 ns; reset <= '0';
wait for 4 ns; enable <= '1';
wait;
end process stimulus;
monitor : process (clk)
variable c_str : line;
begin
if (clk = '1' and clk'event) then
write(c_str,count);
assert false report time'image(now) &
": Current Count Value : " & c_str.all
severity note;
deallocate(c_str);
end if;
end process monitor;
end counter_tb;
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