On Fri, 27 Nov 2009 20:02:45 +0000 Kelvin Gardiner <[email protected]> wrote:
> Hi, > > I've attached a number of patches and new files to add Verilog syntax > highlighting and symbols. I've taken the Verilog lexer directly from > Scintilla. Thanks for the patch & sorry for the slow response. It's now applied in SVN, with some changes: Adjusted some styleset_verilog_init allocations that were too big. Removed the commented VHDL symbols.c lines (not sure what they were for). Added a get.h include to verilog.c to fix build. BTW You might like to use the 'svn diff >patch.diff' command another time as it's probably easier than diffing each file manually ;-) Regards, Nick _______________________________________________ Geany-devel mailing list [email protected] http://lists.uvena.de/cgi-bin/mailman/listinfo/geany-devel
