Steve Meier wrote:
My plan for dealing with long refdes names e.g.S1/S2/S3/U3 is to hide
the refdes and create a large box on the silkscreen which is labled S1.
Then inside the S1 Box, a smaller box on the silcrean labled S2 and
inside ths S2 box an even smaller box labled S3. The device inside the
S3 box will have a silk screened comment near it that states U3.
[jg]Sounds good for fabbing and debugging!
As far as renumbering refdes in a hierarchical design is that I have
added the capability to tell a hierarchical symbol to not adjust the
refdes for components within the symbol. This is needed because a large
FPGA is split among several hierarchical symbols (all on the same level
and having the same root hierarchy e.g the root hierarchy might be S1/S2
and the fgpa split in to symbols labled S3, S4 and S5 but retaining the
same final refdes for the device U1). So in a final netlist, without the
ability to disable refdes adjusting the one fpga becomes: S1/S2/S3/U1
and S1/S2/S4/U1 and S1/S2/S5/U1 which makes pcb think there are three
different devices. Turning off the refdes adjust for S3, S4 and S5
generates the refdes S1/S2/U1 and S1/S2/U1 and S1/S2/U1 which become a
single device at layout time. However, If S3 and S4 have some capacitors
inside their schematics I have to be carefull to make sure that the same
refdes are not used or the caps also become single components
unexpectedly shorting out nets.
Ahh ain't life complex and interesting,
That problem gives me an idea.
What if you made the component be the place to choose whether or not to
drop a hierarchy level so a multipart symbol gets merged? It might work like
this: U1 has three parts, needs merging.
U1 chunks are placed in S1/S2/S3, S1/S2/S5, and S1/S2/S4. Inside each of
those are R1, R2, U1, and C1.
Each of those U1s has an attribute attached that orders the netlister to "lose one level of hierarchy for U1 only. The netlist
will not match the schematics now, it will be as if the inouts/ports/pins of U1 have been moved up to the next level and any nets
connecting U1 inherit the next level up names. That way, R1, R2, and C1 still are unique in their hierarchic cell/module/schematic.
If you did a netlist that way, it would be good to keep an unsmashed one around
too. One that shows the exact connections
through the schematic pins/ports/inouts with all the different possible names across any module boundary. That will help debug
any trouble. The merged netlist that does NOT match the schematic can be made after the more complete one and only from it and
the attribs on U1 chunks.
I think this way I just described would keep more of the benefits of hierarchy.
The benefit that you can reuse stuff
that has the wrong names inside being the main one.
John Griessen
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