Steve Meier wrote:
John,
You are an experienced chip layout guy and so might have an idea about
how to handle multiple layers of hierarchy and refdes numbering. Any
suggestions?
Hi Steve, The chip software from Cadence builds on the concept of layout or
schematic
cell instances that are numbered
at the level of hierarchy they are placed in, and everything has a long trail
of names
to define them. When a flat netlist is made of the whole collection of cells,
some name
shortening is done.
There is never any possibility of meaningful printable names that
appear in the product like in the board silk screen layer, so it's not
a perfect model for refdes's. It's even possible with chip software to make
layout cells that do not match schematic cells, and only match as a
conglomeration
one or two levels up in hierarchy. We will seldom do that on boards of
soldered parts though.
I have made some hierarchic board layout and I just stick with a condensed
naming scheme from the start
where sub-schematics are created for all layout cells and I keep a one to one
correspondence schematic to layout, with a single letter followed by one digit
for names.
I used a letter-number naming scheme for some lightning protection circuits on
a row of inputs recently.
Have not gotten as far as letter plus two digits. At that point, you might as well just not even make the names visible on the
silkscreen layer, and then not condense them either so they have meaning for debugging purposes.
For renumbering, there is nothing to learn from chip work -- they never do that
to a whole section.
Sometimes a set of instances is wiped out and replaced and then just that row
of instances will get new numbers, nothing else.
So my suggestion is to not worry about renumbering as much in your hierarchy
programming -- just make
some way for the netlister to grab all the names like top-1/ADC-1/esd-1/U3-6
where the first three names are
schematics and the last is a component placed in schematic esd-1. Top drawings are not different than any other in the chip
design scheme, since who knows if they will just be placed in another larger chip next... to keep it simple
and allow for automatic schematic symbol generation of all schematics and
sub-schematics the same way.
John Griessen
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