John, My plan for dealing with long refdes names e.g.S1/S2/S3/U3 is to hide the refdes and create a large box on the silkscreen which is labled S1. Then inside the S1 Box, a smaller box on the silcrean labled S2 and inside ths S2 box an even smaller box labled S3. The device inside the S3 box will have a silk screened comment near it that states U3.
As far as renumbering refdes in a hierarchical design is that I have added the capability to tell a hierarchical symbol to not adjust the refdes for components within the symbol. This is needed because a large FPGA is split among several hierarchical symbols (all on the same level and having the same root hierarchy e.g the root hierarchy might be S1/S2 and the fgpa split in to symbols labled S3, S4 and S5 but retaining the same final refdes for the device U1). So in a final netlist, without the ability to disable refdes adjusting the one fpga becomes: S1/S2/S3/U1 and S1/S2/S4/U1 and S1/S2/S5/U1 which makes pcb think there are three different devices. Turning off the refdes adjust for S3, S4 and S5 generates the refdes S1/S2/U1 and S1/S2/U1 and S1/S2/U1 which become a single device at layout time. However, If S3 and S4 have some capacitors inside their schematics I have to be carefull to make sure that the same refdes are not used or the caps also become single components unexpectedly shorting out nets. Ahh ain't life complex and interesting, Steve Meier On Wed, 2007-03-14 at 10:59 -0500, John Griessen wrote: > Steve Meier wrote: > > John, > > > > You are an experienced chip layout guy and so might have an idea about > > how to handle multiple layers of hierarchy and refdes numbering. Any > > suggestions? > > Hi Steve, The chip software from Cadence builds on the concept of layout or > schematic > cell instances that are numbered > at the level of hierarchy they are placed in, and everything has a long trail > of names > to define them. When a flat netlist is made of the whole collection of > cells, some name > shortening is done. > > There is never any possibility of meaningful printable names that > appear in the product like in the board silk screen layer, so it's not > a perfect model for refdes's. It's even possible with chip software to make > layout cells that do not match schematic cells, and only match as a > conglomeration > one or two levels up in hierarchy. We will seldom do that on boards of > soldered parts though. > > I have made some hierarchic board layout and I just stick with a condensed > naming scheme from the start > where sub-schematics are created for all layout cells and I keep a one to one > correspondence schematic to layout, with a single letter followed by one > digit for names. > I used a letter-number naming scheme for some lightning protection circuits > on a row of inputs recently. > > Have not gotten as far as letter plus two digits. At that point, you might > as well just not even make the names visible on the > silkscreen layer, and then not condense them either so they have meaning for > debugging purposes. > > For renumbering, there is nothing to learn from chip work -- they never do > that to a whole section. > Sometimes a set of instances is wiped out and replaced and then just that row > of instances will get new numbers, nothing else. > > So my suggestion is to not worry about renumbering as much in your hierarchy > programming -- just make > some way for the netlister to grab all the names like top-1/ADC-1/esd-1/U3-6 > where the first three names are > schematics and the last is a component placed in schematic esd-1. Top > drawings are not different than any other in the chip > design scheme, since who knows if they will just be placed in another larger > chip next... to keep it simple > and allow for automatic schematic symbol generation of all schematics and > sub-schematics the same way. > > John Griessen > > > _______________________________________________ > geda-dev mailing list > [email protected] > http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev _______________________________________________ geda-dev mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev
