Sub symbol generation for splitting up fpga io pins into symbols that match the requirements of a board's sub-circuits would be very useful.
I could envision a flow of a file which contains a list of io pins, if the pin is part of a pin pair (differential io) and part of a logical block (e.g. pins dedicated for qdr ii dram interface) a method for entering sub-circuit requirements. need interface for qdrii device (or not) number of io pins logic family (lvttl or lvpecl or....) perhaps allow user to select the preferred io bank or side of the chip. have program generate symbols and place them in project folder with unique symbol name such that multiple instances of the same device could be used within a project and not generate conflicting symbol file names. I could also envision a program which given a hierarchical symbol would generate the start of a schematic making sure that the schematic had nets for each symbol pin. This reminds me that the netlister/drc should check to see that nets exist for each io pin. Steve Meier On Wed, 2008-04-02 at 14:45 -0400, Stuart Brorson wrote: > > Now, that the GSoC application deadline was delayed, I'd like to propose > a project that would definitely improve usability of gschem: > > An interactive sub sheet symbol generator > > Currently, manual sub sheet generation is a major obstacle when starting > a hierarchical project. I'd expect this to be a finite project with good > chance to be completed by the end of summer. Any chance for this proposal > to enter the GSoC procedure? > > If you could write it up (include a little more detail in the > write-up) and stick it on the gEDA Wiki, that would be > a good start.... > > Cheers, > > Stuart > > > _______________________________________________ > geda-dev mailing list > [email protected] > http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev _______________________________________________ geda-dev mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev
