On Thu, Feb 03, 2005 at 05:36:48PM +0300, Konstantin Savenkov wrote: > I want to integrate hardware components, written in Verilog, to our > simulation modeling environment. It seems convinient to translate > Verilog module in C++ and use a proper wrapper, which provides the > interface, required by a runtime of the environment. > > I've found in the archive of this list that Icarus Verilog can be used to > translate Verilog source to C++,
That mode of operation was abandoned years ago. > Maybe there is another, more correct way to use Icarus-compiled module in > foreign environment? I use two approaches, depending on the need: If your C/C++/Fortran can be used as a _slave_, a subroutine that gets called by the Verilog simulator, it's easy to link in via PLI. For analog system models, it's easy enough to have the verilog program call the model at periodic virtual intervals. If the other program needs to be a _master_, running its own flow of control, you can communicate between it and Icarus using message passing over a pipe. I do this for hardware-software cosimulation, where the messages represent bus transactions. Examples of both styles of interaction are part of my production Low Level RF package called llc-suite, covered by something close to a 3-clause BSD license, at http://recycle.lbl.gov/llc-suite/ . The pipe-style communication was inspired by Steve Williams' pcisim, an item listed on the Icarus plug-in page at http://icarus.com/eda/verilog/plug-ins.html . I hope this helps. - Larry
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