If your Verilog code falls within the synthesizable subset of Icarus, you can use the Icarus FNF code generator (packaged with Confluence) to build an FNF netlist. From FNF, you can tranlate to other formats (VHDL, JHDL, NuSMV, C).
Currently the FNF->C translation is incomplete, though I should be able to have it up and running in a few weeks. http://www.confluent.org/ The other Verilog-to-C option is Verilator (found on my links page): http://www.confluent.org/wiki/doku.php?id=links -Tom -----Original Message----- From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] Behalf Of Konstantin Savenkov Sent: Thursday, February 03, 2005 8:37 AM To: [EMAIL PROTECTED] Subject: gEDA: How to obtain a generated C++ from Icarus? I want to integrate hardware components, written in Verilog, to our simulation modeling environment. It seems convinient to translate Verilog module in C++ and use a proper wrapper, which provides the interface, required by a runtime of the environment. I've found in the archive of this list that Icarus Verilog can be used to translate Verilog source to C++, although that was a rather old message (2000). I've failed to find any mention about such an ability in Icarus docs. Is it obsolete? Or it is still possible to use Icarus for such a conversion? Maybe there is another, more correct way to use Icarus-compiled module in foreign environment? Konstantin O. Savenkov, Computer Science Dept. of the Moscow State University
