Stephen Williams <[EMAIL PROTECTED]> writes: > The v0.8 releases of Icarus Verilog have decent synthesis. The > synthesis is not at all Xilinx specific, but the code generators > are. But they needn't be. The FPGA target generates EDIF, so if > your intermediate form takes EDIF, the way to move forward is to > work on the fpga code generator to generate code for your device.
Hey, thanks for the advice. I've got 0.8.4 generating EDIF that parses and flattens it into a netlist my PAR tools can handle. One difficulty, though: the primitive cells that iverilog emits are pretty complex. Is there any way to ask it to break down multipliers and adders into stuff no larger than a LUT4? Also, what's the difference between the tgt-edif and tgt-fpga directories? Thanks! - a -- PGP/GPG: 5C9F F366 C9CF 2145 E770 B1B8 EFB1 462D A146 C380 _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
