Please bear in mind that this is only an 8-bit ripple-carry adder, and the tools are still quite crude, but I believe we now have the first-ever instance of a design being taken through a 100% open-source flow, all the way from verilog to blinking lights on a programmed device.
Details are here: http://research.cs.berkeley.edu/project/slipway/ Again, it's nowhere close to production-ready, but there are already a lot of doors opening up: programmatic access to the inner PAR loop (ie incremental runs) plus partial reconfiguration is a very powerful combination. More to come. - a -- PGP/GPG: 5C9F F366 C9CF 2145 E770 B1B8 EFB1 462D A146 C380 _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
