Hi all, I'm consulting for a small ASIC startup that is interested in gEDA. They have a handful of licenses for expensive commercial tools but were looking for a low-overhead way to do some semi-custom work and asked me to investigate. I just went through the process of figuring out how to make symbols for the third-party standard cell libraries they've licensed, and I thought I'd share my experiences since I couldn't find this described on the net anywhere.
Among the provided views of this library are ones for Cadence's Composer product. It turns out Cadence supplies a tool called "edifout", which will produce an EDIF (text) version of any cell view. You need to supply a template file, which Cadence helpfully provides an example of (tools/dfII/samples/xlUI/edifOut.il). I wrote a Perl script that just runs this once for every cell in the library, although some people recommend building a huge schematic with every cell in it, and then running edifout just once. With my approach you do need to generate a new template file each time, specifying a different cell (and you want the "symbol" view). Now you have EDIF for each cell's symbol view. From here I tried to find some kind of public-domain parser, but everything was a dead end. Then I realized that EDIF looked kind of like Lisp - i.e., an "s-expression". It turns out there's a CPAN module for parsing s-expressions called Data::SExpression, so I could suck in the whole file and treat it as a data structure (lists of lists). I did have to do a few day's worth of coding on top of this to generate the gschem symbols - the EDIF can be complex and the vendor libraries are quirky. Here are a few difficulties I encountered: 1) gschem wants pins to always be "pins" - i.e., a single line segment with a connection point at one end. EDIF has a "connection point" concept, but that point can be anywhere on a line segment or arc. 2) converting arcs was a challenge for me. gEDA wants (center, radius, start angle, sweep angle) while EDIF supplies three points known to be on the arc. You have to convert. I found the Wikipedia article called "Circle" to be the most helpful reference. 3) It seems like the gnetlist backends for Spice and Verilog have different concepts of how ports (for example) are specified, and possibly other things as well. It's desirable to have a single schematic netlistable to either format, but I don't think that works right now. So that's what I did. I wouldn't be surprised if there are better approaches - would anyone care to comment? I'd also be interested in hearing from anyone else out there who's tried to apply gEDA to ASIC design. Regards, Jeff Trull _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
