On Sunday 20 January 2008, a r wrote: > Is it possible to setup gnetlist (gnetlist -g spice-sdb) so > that it won't add ".END" at the end of the spice netlist? > > In my flow, I usually prepare a testbench file manually and > from here I include a (clean, without simulation commands) > netlist. However, that ".END" makes this flow awkward. Sure, > I can do it the other way around or postprocess the netlist > but it's an additional hassle.
I usually need to edit the generated netlist. If not this, it is something else. I also usually need to do the schematic in a way a little different than I want, to make the netlister happy. The other netlisters have problems too .. The Verilog netlister does not pass attributes. The VHDL netlister gets the pin names wrong. _______________________________________________ geda-user mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
